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參數(shù)資料
| 型號： | CLDLTSJ-312.500 |
| 廠商： | RALTRON ELECTRONICS CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 312.5 MHz, LVDS OUTPUT |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 54K |
| 代理商： | CLDLTSJ-312.500 |
CLOCK
Page 1 of 3
RAL T RON EL ECT R ONICS CORP.
! 10651 N . W . 19
th St ! Mi ami, Florida 33172 ! U.S.A.
phone: (305) 593-6033
! fax: (305) 594-3973 ! e-mail: sales@raltron.com ! WEB: http://www.raltron.com
CLDL/CLDPL SERIES: ULTRA HF CLOCK OSCILLATOR, LVDS, +3.3 VDC or +2.5VDC
DESCRIPTION: A crystal controlled, high frequency, highly stable oscillator, adhering to Low Voltage Differential Signaling
(LVDS) Standards. The output can be Tri-stated to facilitate testing or combined multiple clocks. The device is contained in a
sub-miniature, very low profile, leadless ceramic SMD package with 6 gold contact pads. This miniature oscillator is ideal for
today's automated assembly environments.
APPLICATIONS AND FEATURES:
"
Infiniband; Fiber Channel; SATA; 10GbE; Network Processors; SOHO Routing; Switches;
"
Common Frequencies: 150 MHz; 156.25 MHz; 155.52 MHz; 161.1328 MHz; 212.5MHz; 312.5MHz
"
+3.3 VDC or +2.5VDC LVDS
"
Frequency Range from 150.000 to 320 MHz
"
Analog multiplication
"
Miniature Ceramic SMD Package Available on Tape and Reel
" Lead Free and ROHS Compliant
$
$ ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNIT
Operating temperature range
Ta
-40…+85
°C
Storage temperature range
T(stg)
-55…+90
°C
Supply voltage
Vcc
+4.6
VDC
Maximum Input Voltage
Vi
Vss-0.5…Vcc+0.5
VDC
Maximum Output Voltage
Vo
Vss-0.5…Vcc+0.5
VDC
$
$ ELECTRICAL PARAMETERS:
PARAMETER
SYMBOL
TEST CONDITIONS
*1
VALUE
UNIT
Nominal Frequency
fo
150.000 ~ 320.00**
MHz
Supply Voltage
Vcc
+3.3 or +2.5
±5%
VDC
Supply Current
Is
80.0 MAX
mA
Output Logic Type
LVDS
Load
Connected between Out and Complementary Out
100
Voh
Output logic high
1.43 Typ, 1.6 Max
VDC
Vol
Output logic low
0.9 Min, 1.10 Typ
VDC
Vod
Differential output
247 Min, 330 Typ, 454 Max
mV
Differential output error
50 Max
mV
VOS
Offset Voltage
1.125 Min, 1.25 Typ, 1.375 Max
VDC
Output Voltage Levels
OS
Offset error
25 Max
mVDC
Duty Cycle
DC
Measured at 50% of Vcc
40/60 to 60/40 or 45/55 to 55/45
%
Rise / Fall Time
tr / tf
Measured at 20/80% and 80/20% Vcc Levels
0.7 TYP 1.0 MAX
*2
ns
Integrated Phase tji RMS, Fj = 12 kHz…20 MHz
5
0.3 TYP**
ps
Integrated Phase RMS tii offset frequency 50KHz to
80MHz
5
0.5 TYP**
ps
Deterministic period Jitter Dj using wavecrest
analyzer
4
1 TYP **
ps
Random period Jitter Rj using wavecrest analyzer
4
2.5 TYP **
ps
Jitter
J
Acumm. Peak to Peak Jitter Tp-p using wavecrest
analyzer
*4
25 TYP**
ps
Phase Noise
(
f)
typ. @212.5MHz
6
f=10 Hz
f=100 Hz
f=1 KHz
f=10 KHz
f=100 KHz
f>1M Hz
-65
-95
-125
-140
-145
-148
dBc/Hz
2X Multip.
-50
Sub Harmonics
f_sub
Load, nom, Supply nom
4X Multip.
-35
dBc
Overall Frequency Stability
f/fc
Op. Temp., Aging, Load, Supply and Cal. Variations
±20, ±25, ±50, or ±100 MAX*3
ppm
Pin 1
Output Enabled
Output Disabled
En
Dis
High Voltage or No Connect
Ground
0.7
Vcc MIN
0.3
Vcc MAX
VDC
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