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參數資料
| 型號： | CM42-67025V-55 |
| 廠商： | ATMEL CORP |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 55 ns, CQCC84 |
| 封裝： | LCC-84 |
| 文件頁數： | 1/23頁 |
| 文件大?。?/td> | 257K |
| 代理商： | CM42-67025V-55 |
M 67025
MATRA MHS
Rev. D (29/09/95)
1
Introduction
The M 67025 is a very low power CMOS dual port static
RAM organised as 8192
× 16. The M 67025 is designed
to be used as a stand-alone 16 bit dual port RAM or as a
combination MASTER/SLAVE dual port for 32 bit or
more
width
systems.
The
MATRA-MHS
MASTER/SLAVE dual port approach in memory system
applications results in full speed, error free operation
without the need of an additional discrete logic.
Master and slave devices provide two independant ports
with separate control, address and I/O pins that permit
independant, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the on-chip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eigh transistors (8T) memory cell and
fabricated with the state of the art 0.65
lithography
named SCMOS, the M 67025 combines an extremely low
standby supply current (typ = 1.0
A) with a fast access
time at 20 ns over the full temperature range. All versions
offer battery backup data retention capability with a
typical power consumption at less than 5
W.
For military/space applications that demand superior
levels of performance and reliability the M 67025 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D Fast access time : 20/25/30/35/45/55 ns
D Wide temperature range :
–55
°C to +125 °C
D 67025 L low power
67025 V very low power
D Separate upper byte and lower byte control for multiplexed
bus compatibility
D Expandable data bus to 32 bits or more using master/slave
chip select when using more than one device
D On chip arbitration logic
D Versatile pin select for master or slave :
– M/S = H for busy output flag on master
– M/S = L for busy input flag on slave
D INT flag for port to port communication
D Full hardware support of semaphore signaling between ports
D Fully asynchronous operation from either port
D Battery back-up operation : 2 V data retention
D TTL compatible
D Single 5 V ± 10 % power supply
D For 3.3 V version, please consult sales
8 K
× 16 CMOS Dual Port RAM
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