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參數資料
| 型號： | CMZ1601-7PD8AHFU |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | 168.50 X 111.20 MM, 38.70 MM HEIGHT, METAL, CASE M02, MODULE |
| 文件頁數： | 10/24頁 |
| 文件大小： | 536K |
| 代理商： | CMZ1601-7PD8AHFU |
Rugged Environment
DC-DC Converters <100 W
M-Family
Edition 2/96 - Melcher AG
7 - 19
MELCHER
The Power Partners.
7.1
0
1
0.95
0
U
i [V DC]
0
t
low min
4
t
low min
4
t
high min
t
h
1
U
ti +Uhi
U
ti
Input voltage failure
Switch-on cycle
Input voltage sag
Switch-on cycle and subsequent
input voltage failure
U
D high
U
D low
U
D
0
JFET
NPN
t
U
o1
U
o1 nom
U
D high
U
D low
U
D
t
low min
4
t
h
1
0
U
D high
U
D low
U
D
0
JFET
NPN
U
o1
U
D high
U
D low
U
D
t
low min
4
U
to
Output voltage failure
0
I
D high
I
D low
I
D
t
0
I
D high
I
D low
I
D
t
2
33
U
o1 nom
U
to +Uho
Input voltage monitoring
Output voltage monitoring
Threshold tolerances and hysteresis:
If
Ui is monitored, the internal input voltage after the input
filter and rectifier (E/LM and LMZ types) is measured. Con-
sequently this voltage differs from the voltage at the con-
nector pins by the voltage drop
U
ti across input filter and
rectifier. The threshold level of the D0 and D9 options is fac-
tory adjusted at nominal output current
Io nom and at TA =
25
°C. The value of Uti depends upon the input voltage
range (AM, BM, ...), threshold level
Ut, temperature and in-
put current. The input current is a function of the input volt-
age and the output power.
Fig. 20
Relationship between Ui, Uo1, UD, ID and Uo1/Uo nom versus time.
1 See "El. output data", for hold-up time.
2 With output voltage monitoring the hold-up time th = 0
3 The D signal remains high if the D output is connected to
an external source.
4 tlow min = 40...200 ms, typically 80 ms
U
ti
U
hi
U
D low
U
D
U
D high
U
i
P
o
=
P
o
nom
P
o
=
0
P
o
=
0
U
ti
P
o
=
P
o
nom
Fig. 19
Definition of Uti,
Uti and Uhi (JFET output)
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