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參數資料
| 型號： | CP82C82 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS Octal Latching Bus Driver |
| 中文描述： | CMOS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 103K |
| 代理商： | CP82C82 |
4-274
March 1997
82C82
CMOS Octal Latching Bus Driver
Features
Full Eight-Bit Parallel Latching Buffer
Bipolar 8282 Compatible
Three-State Noninverting Outputs
Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Single 5V Power Supply
Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10
μ
A
Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
Ordering Information
PART NUMBER
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
PACKAGE
PKG. NO.
CP82C82
20 Ld PDIP
E20.3
IP82C82
CS82C82
20 Ld PLCC
N20.35
IS82C82
CD82C82
20 Ld CERDIP
F20.3
ID82C82
MD82C82/B
8406701RA
SMD #
MR82C82/B
-55
o
C to +125
o
C 20 Pad CLCC
J20.A
84067012A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
7
DI
6
OE
GND
V
CC
DO
1
DO
2
DO
3
DO
0
DO
4
DO
5
DO
6
DO
7
STB
19
3
2
20
1
15
16
17
18
14
9
10
11
12
13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
O
G
S
D
7
D
6
DO
2
DO
3
DO
4
DO
5
DO
1
D
2
D
1
D
0
V
C
D
0
TRUTH TABLE
STB
OE
DI
DO
X
H
X
Hi-Z
H
L
L
L
H
L
H
H
↓
L
X
H
L
X
= Logic One
= Logic Zero
= Don’t Care
= Latched to Value of Last
Data
Hi-Z = High Impedance
↓
= Neg. Transition
PIN NAMES
PIN
DESCRIPTION
DI
0
-DI
7
DO
0
-DO
7
STB
Data Input Pins
Data Output Pins
Active High Strobe
OE
Active Low Output
Enable
File Number
2975.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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