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參數資料
| 型號： | CS1001-7ERV0TB1 |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE S02, MODULE |
| 文件頁數： | 22/33頁 |
| 文件大小： | 438K |
| 代理商： | CS1001-7ERV0TB1 |
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S Series Data Sheet
100 Watt AC-DC and DC-DC Converters
APR 26, 2006 revised to SEP 25, 2006
Page 29 of 33
www.power-one.com
Table 23: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment range
Typical hysteresis
Vh [% of Vt]
(VME compatible)
of threshold level
Vt
for
Vt min - Vt max
Vi
Vo1
Vti
Vto
Vhi
Vho
V2
yes
no
Vi min - Vi max
1
–
3.4 - 0.4
–
V3
yes
Vi min - Vi max
1
0.95 - 0.985
Vo1
2
3.4 - 0.4
"0"
V0
yes
no
Vi min - Vi max
3, 4
–
3.4 - 0.4
–
yes
Vi min - Vi max
3, 4
0.95 - 0.985
Vo1
2
3.4 - 0.4
"0"
1 Threshold level adjustable by potentiometer.
2 Fixed value between 95% and 98.5% of Vo1 (tracking).
3 Adjusted at Io nom.
4 Fixed value, resistor-adjusted (±2% at 25 °C) acc. to customer's specifications; individual type number is determined by Power-One.
Table 22: Available internal input capacitance and factory potentiometer setting of Vti with resulting hold-up time
Types
AS
BS
FS
CS
DS
ES
LS
Unit
Ci min
0.83
0.3
1.2
0.66
0.26
0.21
mF
Vt i
9.5
19.5
39
61
97
120
VDC
th
0.1
5.3
1.9
1.8
4.3
6.4
ms
Option V: ACFAIL Signal (VME)
Available only for models with Vo = 5.1 V.
This option defines an undervoltage monitoring circuit for the
input and main output voltage. It generates an ACFAIL signal
(V signal) which conforms to the VME standard.
The low state level of the ACFAIL signal is specified at a sink
current of IV ≤ 48 mA to VV ≤ 0.6 V (open-collector output of an
NPN transistor). The pull-up resistor feeding the open-collector
output should be placed on the VME backplane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time (th) of at least 4 ms before the 5.1 V
output drops to 4.875 V when the output is fully loaded. The
hold-up time is provided by the internal input capacitance.
Consequently, the working input voltage and the threshold level
(Vti) should be adequately above the minimum input voltage
(Vi min) of the converter so that enough energy is remaining in
the input capacitance. If the input voltage is below the required
level, an external hold-up capacitor (Ci ext) should be added.
Formula for threshold level for desired value of
th:
2
Po (th + 0.3 ms) 100
Vti =
––––––––––––––––––––– +
Vi min
2
Ci min η
Formula for the external input capacitor:
2
Po (th + 0.3 ms) 100
Ci ext = –––––––––––––––––––––– – Ci min
η (Vti 2 – Vi min2)
where as:
Ci min = internal input capacitance [mF]
Ci ext = external input capacitance [mF]
Po
= output power [W]
η
= efficiency [%]
th
= hold-up time [ms]
Vi min = minimum input voltage [V] 1
Vti
= threshold level [V]
1 Min. input voltage according to Electrical Input Data. For output voltages
Vo > Vo nom, the minimum input voltage increases proportionally to
Vo/Vo nom.
Remarks:
Option V2 and V3 can be adjusted by potentiometer to a threshold
level between Vi min and Vi max. A decoupling diode should be
connected in series with the input of AS - FS converters to avoid
the input capacitance discharging through other loads connected
to the same source voltage.
Vt + Vh. The threshold level Vti is either adjustable by
potentiometer, accessible through a hole in the front cover,
or adjusted during manufacture to a determined customer
specified value.
Versions V0, V2, and V3 are available as shown below.
Option V operates independently of the built-in input
undervoltage lockout circuit. A logic "low" signal is generated at
pin 20 as soon as one of the monitored voltages drops below the
preselected threshold level
Vt. The return for this signal is Vo1–.
The V output recovers when the monitored voltage(s) exceed(s)
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