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參數(shù)資料
| 型號： | CS5102A-JLZ |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 英文描述： | 16-bit, 100 kSps / 20 kSps A/D Converters |
| 中文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28 |
| 封裝： | MS-047, LCC-28 |
| 文件頁數(shù)： | 1/39頁 |
| 文件大?。?/td> | 491K |
| 代理商： | CS5102A-JLZ |
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Copyright
Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
CS5101A
CS5102A
16-bit, 100 kSps / 20 kSps A/D Converters
Features
z
Monolithic CMOS A/D Converters
– Inherent Sampling Architecture
– 2-channel Input Multiplexer
– Flexible Serial Output Port
z
Ultra-low Distortion
– S/(N+D): 92 dB
– TDH: 0.001%
z
Conversion Time
– CS5101A: 8
μ
s
– CS5102A: 40
μ
s
z
Linearity Error:
±
0.001% FS
– Guaranteed No Missing Codes
z
Self-calibration Maintains Accuracy
– Accurate Over Time & Temperature
z
Low Power Consumption
– CS5101A: 320 mW
– CS5102A: 44 mW
Description
The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters (ADCs) capable of
100 kSps (5101A) and 20 kSps (5102A) throughput. The
CS5102A’s low power consumption of 44mW, coupled
with a power-down mode, makes it particularly suitable
for battery-powered operation.
On-chip self-calibration circuitry achieves nonlinearity of
±0.001% of FS and guarantees 16-bit, no missing codes
over the entire specified temperature range. Superior lin-
earity also leads to 92 dB S/(N+D) with harmonics below
-100 dB. Offset and full-scale errors are minimized dur-
ing the calibration cycle, eliminating the need for external
trimming.
The CS5101A and CS5102A each consist of a 2-chan-
nel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architec-
ture of the device eliminates the need for an external
track-and-hold amplifier.
The converters’ 16-bit data is output in serial form with
either binary or two’s complement coding. Three output
timing modes are available for easy interfacing to micro-
controllers and shift registers. Unipolar and bipolar input
ranges are digitally selectable
ORDERING INFORMATION
See
“Ordering Information” on page 38
.
I
CLKIN
XOUT
REFBUF
VREF
AIN1
AGND
HOLD SLEEPRST
CODEBP/UP
TRK1TRK2 SSH/SDLSDATA
SCLK
TEST
DGND
VD-
VD+
VA-
VA+
12
28
2
5
16
17
8
9
11
15
3
4
21
20
19
22
25
23
7
1
6
26
14
-
+
-
+
-
+
-
+
Comparator
Clock
Generator
Control
Calibration
SRAM
Microcontroller
16-Bit Charge
Redistribution
DAC
STBY
CRS/FIN
10
AIN2
24
CH1/2
13
SCKMOD
27
OUTMOD
18
JAN ‘06
DS45F6
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| CS5101EDWR16G | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters |
| CS5101EN14G | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters |
| CS5101 | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters(用于AC/DC和DC/DC多輸出轉(zhuǎn)換器的次級邊后調(diào)整器) |
| CS51021A | Enhanced Current Mode PWM Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5102A-JP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-Bit, 100kHz/ 20kHz A/D Converters |
| CS5102A-KL | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-Bit, 100kHz/ 20kHz A/D Converters |
| CS5102A-KP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-Bit, 100kHz/ 20kHz A/D Converters |
| CS5102-AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
| CS5102A-SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
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