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參數資料
| 型號： | CS5376 |
| 元件分類： | 串行ADC |
| 英文描述： | CS5376 Rev. A Errata|Geophysical|A/D Converters |
| 中文描述： | CS5376版本A勘誤表|地球物理| A / D轉換 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 171K |
| 代理商： | CS5376 |
Cirrus Logic
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
ER256A1
AUG ‘01
1
09/05/01
Errata: CS5376 Rev. A
(Reference CS5376 Data Sheet revision DS256PP1 dated Jan ‘01)
Introduction
The CS5376 is a low power multi-channel digital filter with integrated system peripherals.
It uses a coefficient programmable signal processing architecture to provide filtering for up
to four
Σ
modulators. Integrated peripherals simplify system design with a buffered
high speed serial data output port, a test bit stream generator suitable for driving a test
DAC, general purpose I/O pins for local hardware control, a secondary master mode SPI
port for serial peripherals, and a JTAG port for boundary scan testing. In addition, a clock
and synchronization block synchronizes the CS5376 to the host system, and a time break
controller generates timing reference information in the output data stream.
Contents
Erratum 1: “SDTKI signal timing into the SD port” on page 1
Erratum 2: “EEPROM configuration loader preamble” on page 5
1.
SDTKI signal timing into the SD port
After filtering is completed, each 24-bit output sample is combined with an 8-bit status
word. This 32-bit data word is written to an 8-deep FIFO buffer and then transmitted to the
communications interface through the high speed serial data output port (SD port). The SD
port can operate in two configurations, a continuous output configuration where data is
output immediately when ready, or a requested output configuration where data is output
only when polled by the communications controller.
Continuous Output SD Port Configuration
The continuous output SD port configuration requires the SDTKI pin to receive continuous
rising edges. A simple method for generating rising edges on SDTKI is to connect it to a 4
MHz or slower system clock. Whenever output data is available from the decimation
engine, a rising edge on SDTKI initiates an SD port transaction.
Once an SD port transaction starts, the SDTKI signal must be gated off to ensure no rising
edges occur during the transaction. The easiest way to guarantee this is to gate the SDTKI
input signal with the SDRDY output signal using an AND gate. When an SD port
transaction starts, the SDRDY signal is driven low by the CS5376 which will gate off the
SDTKI input. When the SD port transaction is complete, the SDRDY signal automatically
returns high to re-enable the SDTKI input.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CS5376A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-power, Multi-channel Decimation Filter |
| CS5376A-IQ | 功能描述:特殊用途放大器 LP Multi-Ch. Decimation Filter RoHS:否 制造商:Texas Instruments 通道數量:Single 共模抑制比（最小值）: 輸入補償電壓: 工作電源電壓:3 V to 5.5 V 電源電流:5 mA 最大功率耗散: 最大工作溫度:+ 70 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-20 封裝:Reel |
| CS5376A-IQR | 功能描述:特殊用途放大器 LP Multi-Ch. Decimation Filter RoHS:否 制造商:Texas Instruments 通道數量:Single 共模抑制比（最小值）: 輸入補償電壓: 工作電源電壓:3 V to 5.5 V 電源電流:5 mA 最大功率耗散: 最大工作溫度:+ 70 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-20 封裝:Reel |
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