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參數資料
| 型號： | CS5571 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | 【2.5 V / 5 V, 100 kSps, 16-bit, High-throughput ツヒ ADC |
| 中文描述： | 【2.5伏/ 5伏，100 kSPS的，16位，高通量ツヒ模數轉換器 |
| 文件頁數： | 1/32頁 |
| 文件大小： | 557K |
| 代理商： | CS5571 |
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Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
Cirrus Logic, Inc. 2007
(All Rights Reserved)
http://www.cirrus.com
6/25/07
14:12
CS5571
±
2.5 V / 5 V, 100 kSps, 16-bit, High-throughput
Σ
ADC
Features
& Description
Single-ended Analog Input
On-chip Buffers for High Input Impedance
Conversion Time = 10
μ
S
Settles in One Conversion
Linearity Error = 0.0007%
Signal-to-Noise = 92 dB
S/(N + D) = 91 dB
DNL = ±0.1 LSB Max.
Self-calibration:
- Maintains accuracy over time & temperature.
Simple three/four-wire serial interface
Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V
- Analog: ±2.5V; IO: +1.8V to +3.3V
Power Consumption:
- ADC Input Buffers On: 85 mW
- ADC Input Buffers Off: 60 mW
General Description
The CS5571 is a single-channel, 16-bit analog-to-digital
converter capable of 100 kSps conversion rate. The input
accepts a single-ended analog input signal. On-chip buff-
ers provide high input impedance for both the AIN input
and the VREF+ input. This significantly reduces the drive
requirements of signal sources and reduces errors due to
source impedances. The CS5571 is a delta-sigma convert-
er capable of switching multiple input channels at a high
rate with no loss in throughput. The ADC uses a low-laten-
cy digital filter architecture. The filter is designed for fast
settling and settles to full accuracy in one conversion. The
converter's 16-bit data output is in serial format, with the
serial port acting as either a master or a slave. The convert-
er is designed to support bipolar, ground-referenced
signals when operated from ±2.5V analog supplies.
The CS5571 uses self-calibration to achieve low offset and
gain errors. The converter achieves a S/N of 92 dB. Linear-
ity is 0.0007% of full scale.
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard logic
operating from 1.8, 2.5, or 3.3 V.
ORDERING INFORMATION:
See
Ordering Information
on page 31.
AIN
ACOM
CS
SCLK
SMODE
VREF+
VREF-
RDY
OSC/CLOCK
GENERATOR
CONV
CAL
BP/UP
CALIBRATION
MICROCONTROLLER
SERIAL
INTERFACE
ADC
DIGITAL
FILTER
LOGIC
VL
MCLK
SDO
RST
DITHER
DCR
VLR
V1-
V2-
BUFEN
V2+
V1+
CS5571
TST
JUN ‘07
DS768A5
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