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參數(shù)資料
型號: CS61581
廠商: Cirrus Logic, Inc.
英文描述: T1/E1 Universal Line Interface
中文描述: 通用的T1/E1線路接口
文件頁數(shù): 1/37頁
文件大小: 810K
代理商: CS61581
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
(All Rights Reserved)
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS61581
T1/E1 Universal Line Interface
Features
Provides T1 and E1, Long Haul and Short
Haul Line Interface
Provides a QRSS Test Signal and Error
Detector
Impedance Matching Line Driver Using a
Single Transformer
Greater than 14 dB of Transmit Return Loss
Without Using External Resistors
No Crystal Needed for Jitter Attenuation
Meets AT&T 62411 and TBR 12/13 Jitter
Tolerance and Attenuation Requirements
Meets ANSI T1.231B and ITU-T G.775
Requirements for LOS and AIS
Meets the BS6450 Transmitter Short-Circuit
Requirements for E1 Applications
Compliant with:
– ITU-T Recommendations: G.703, G.732,
G.775 and I.431
– American National Standards (ANSI): T1.102,
T1.105, T1.403, T1.408, and T1.231
– FCC Rules and Regulations: Part 68 and Part
15
– AT&T Publication 62411
– ETSI ETS 300 011, 300 233, TBR 12/13
– TR-NET-00499
Description
The CS61581 is a primary rate line interface unit capa-
ble of operation in both short haul (intraoffice) and long
haul applications. The CS61581 combines the com-
plete analog transmit and receive circuitry for a single,
full-duplex interface at T1 and E1 rates. The device is
pin and function compatible with the Level One LXT310
and LXT318 (the latter in the host mode only). The de-
vice can also replace LXT359 and LXT360. Enhanced
functionality is available through an extended register
set allowing short haul operation, custom pulse shape
generation, QRSS pattern generation, detection and er-
ror counting, and generation and detection of loop up
and loop down codes. The CS61581 features Crystal
low-power impedance-matched line drivers and crystal-
less jitter attenuation.
ORDERING INFORMATION
CS61581-IL
CS61581-IP
28-pin PLCC
28-pin PDIP
DS211PP8
DS211F1
TCLK
TDATA/TPOS
UBS/TNEG
JASEL
RCLK
RDATA/RPOS
BPV/RNEG
INT/NLOOP
LOS
2
3
4
E
N
C
O
D
E
R
11
Q
R
S
S
REMOTE
LOOPBACK
8
7
6
D
E
C
O
D
E
R
23
12
NLOOP
& LOS
PROCESSOR
RECEIVE
GECLOCK
9
10
XTALIN
XTALOUT
5
21
22
14
15
MODE
RV+
RGND TGND
TV+
JITTER
ATTEN
TIMING
RECOVERY
LOS/
NLOOP
Clear
REGISTERS & CONTROL LOGIC
TAOS Enable
LBO Select
JITTER
ATTEN
TRANSMIT
TIMING &
PULSE
SHAPING
CIRCUITRY
ROM / RAM
LINE DRIVERS
PORT
LLOOP
Enable
LOCAL
(ANALOG)
SH/LH
EQUALIZER
CONTROL
SLICERS
DETECT
CNOISE &
FILTERS
SH
MAGNITUDE
EQUALIZER
AGC
SH
13
16
28
26
27
24
25
18
19
20
1
TTIP
TRING
CLKE/TAOS
CS/RLOOP
SCLK/LLOOP
SDI/LBO1
SDO/LBO2
LATN
RTIP
RRING
MCLK
LLOCAL
(DIGITAL)
Copyright
Cirrus Logic, Inc. 2005
http://www.cirrus.com
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