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參數資料
| 型號： | CS62LS4008HI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | Low Power CMOS SRAM 512K X 8 Bits |
| 中文描述： | 低功耗CMOS SRAM為512k × 8位 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 532K |
| 代理商： | CS62LS4008HI |
Low Power CMOS SRAM
512K X 8 Bits
UC62LS4008
-20/-25
Features:
Vcc operation voltage : 3.0V ~ 3.6V
Low power consumption :
20mA (Max.) operating current
2uA (Typ.) CMOS standby current
High Speed Access time :
25ns (Max.) at Vcc = 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.2V
Easy expansion with CE\ and OE\ options
Description
The UC62LV2008 is a high performance, very low power
CMOS Static Random Access Memory organized as 524,288
words by 8 bits and operates from 3.0V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 2uA and maximum access
time of 25ns in 3.0V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LS4008 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The UC62LS4008 is available in the JEDEC standard 32
pin 450mil Plastic SOP, 8mmx20.0mm TSOP (type I),
and 8mmx13.4mm STSOP.
PRODUCT FAMILY
Power Consumption
STANDBY
Vcc=3.3V(Typ.)
Speed
(ns)
Operating
Vcc=3.6V(Max.)
Product Family
Operating
Tempature
Vcc Range
Vcc=3.0V(Max.)
Package
Type
UC62LS4008HC
UC62LS4008FC
UC62LS4008GC
UC62LS4008AC
UC62LS4008HI
UC62LS4008FI
UC62LS4008GI
UC62LS4008AI
PIN CONFIGURATIONS
TSOP-32
SOP-32
STSOP-32
DICE
TSOP-32
SOP-32
STSOP-32
DICE
0
~ 70
3.0V ~ 3.6V
20/25
2uA
20mA
-40
~ 85
3.0V ~ 3.6V
20/25
2uA
20mA
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VCC
A15
A18
28
27
26
25
24
23
22
21
20
19
18
17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
16
11
12
13
14
15
16
CS62LS4008HC
CS62LS4008GI
29
30
31
32
CS62LS4008FI
A17
A16
1
2
3
4
5
6
7
8
9
10
A0
A1
DQ0
DQ1
DQ2
GND
A14
A12
A7
A6
A5
A4
A3
A2
A16
A18
A15
VCC
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
CS62LS4008HI
CS62LS4008GC
BLOCK DIAGRAM
MEMORY ARRAY
512K X 8 Bits
R
D
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X8
I/O BUFFER
A
B
C
B
C
I
B
COL
Address
ROW
Address
CE
WE
OE
A
CE
WE
OE
D
D
D
D
D
D
D
D
U-Chip Technology Corp. LTD. .
Reserves the right to modify document contents without notice.
Preliminary
Rev.1.0
PAGE
1
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