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參數(shù)資料
| 型號： | CS91 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Standard cell array |
| 中文描述： | 標(biāo)準(zhǔn)單元陣列 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 53K |
| 代理商： | CS91 |
DS06-20208-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright2002-2006 FUJITSU LIMITED All rights reserved
Semicustom
CMOS
Standard cell array
CS91 Series
■
DESCRIPTION
The CS91 series 0.11
μ
m CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed
and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16
ps, resulting in both integration and speed about three times higher than conventional products.
■
FEATURES
Technology
: 0.11
μ
m silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) ,
Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity)
Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip.
Supply voltage
:
+
1.2 V
±
0.1 V (standard specification)
Junction temperature range :
40
°
C to
+
125
°
C
Gate delay time : t
pd
=
16 ps (1.2 V, inverter, F/O
=
1)
Gate power consumption : Pd
=
6.6 nW/MHz/BC (1.2 V, inverter, F/O
=
1)
Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for
transmission
Special interfaces* : P-CML, LVDS, PCI, SSTL, HSTL, T-LVTTL, and others.
Buffer cell dedicated to crystal oscillator
IP macros*
: CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others.
Compiled cells (RAM/ROM/multiplier, and others.)
Uses industry standard tools and supports the optimum tools for the application
Short-term development using a physical prototyping tool
Hierarchical design environment for supporting large-scale circuits
Support for SIGNAL INTEGRITY, EMI noise reduction
Support for High resolution RC extraction base delay calculation environment
Support for optimization environment of power supply wire
(Continued)
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