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參數資料
| 型號： | CSP2510D |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 3.3鎖相環時鐘驅動器零延遲緩沖器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 72K |
| 代理商： | CSP2510D |
1
0
°
C TO 85
°
C TEMPERATURE RANGE
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
OCT OBER 2001
2001 Integrated Device Technology, Inc.
DSC-5874/2
c
IDTCSP2510D
0oC T O 85oC T EMPERAT URE RANGE
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
ZERO DELAY BUFFER
DE S CRIPT ION:
The CSP2510D is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510D
operates at 3.3V.
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the control G input.
When the G input is high, the outputs switch in phase and frequency with
CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSP2510D does not require
external RC networks. The loop filter for the PLL is included on-chip,
mnimzing component count, board space, and cost.
Because it is based on PLL circuitry, the CSP2510D requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AV
DD
to ground.
The CSP2510D is specified for operation from0°C to +85°C. This device
is also available (on special order) in Industrial temperature range (-40°C
to +85°C). See ordering information for details.
21
Y9
PLL
3
5
8
9
4
Y0
Y1
Y2
Y3
Y4
15
17
20
16
Y5
Y6
Y7
Y8
24
13
23
AV
DD
FBIN
CLK
G
11
12
FBOUT
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
Distributes one clock input to one bank of ten outputs
Output enable bank control
External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
No external RC network required for PLL loop stability
Operates at 3.3V V
DD
tpd Phase Error at 166MHz: < ±150ps
Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
Spread Spectrum Compatible
Operating frequency 50MHz to 175MHz
Available in 24-Pin TSSOP package
APPLICATIONS:
SDRAMModules
PC Motherboards
Workstations
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CSP2510DPG | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Driver Single 50MHz to 175MHz 24-Pin TSSOP Tube 制造商:Integrated Device Technology Inc 功能描述:10 + 1 Outputs 3.3V PLL Clk Driver PC133 |
| CSP2510DPG8 | 功能描述:鎖相環 - PLL 10 + 1 Outputs 3.3V PLL Clk Driver PC133 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CSP2510DPGG | 功能描述:時鐘驅動器及分配 10 + 1 Outputs 3.3V PLL Clk Driver PC133 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CSP2510DPGG8 | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CSP2510DPGGI | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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