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參數(shù)資料
| 型號： | CW901101 |
| 廠商： | LSI Corporation |
| 英文描述： | 10-Bit 45MSPS Pipelined ADC Core(45MSPS、10位管線型A/D轉(zhuǎn)換器) |
| 中文描述： | 10位45MSPS流水線ADC的核心（45MSPS，10位管線型的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 242K |
| 代理商： | CW901101 |
Overview
The CW901101 is a high-performance 10-bit 45MSPS analog-to-digital converter
(ADC) core targeted for digital receivers of cable modems, digital set-top boxes
or digital TVs (DTV). The core is compatible with LSI Logic’s FlexStream
ASIC design environment to enable seamless integration of the mixed-signal
core into complex ASICs. Proven in silicon, this core allows customers to reduce
time to market while providing cost reductions by integrating the ADC on chip.
The complex, high frequency QAM IF signals received by digital receivers are
generally downconverted or directconverted in the analog domain and then
digitized using a high-speed ADC. They are then filtered and demodulated for
further digital signal processing. Sampling techniques such as oversampling and
undersampling are used to convert the analog QAM IF signals to a high resolu-
tion 10-bit parallel stream. Whether an application requires undersampling or
oversampling, the ADC must deliver high levels of dynamic performance. The
overall system performance will depend on the ADC’s dynamic parameters
including spurious-free dynamic range (SFDR), total harmonic distortion (THD)
and signal-to-noise ratio (SNR) or signal-to-noise and distortion ratio (SINAD).
The CW901101 core employs a pipelined architecture and meets the high signal
integrity, bandwidth and sampling speeds necessary to digitize the incoming
signals for 256-QAM or OFDM demodulation. Power consumption and core
size have been optimized with performance to create an attractive solution for
digital receivers.
CW901101 10-Bit Pipelined ADC Core
The CW901101 ADC Core
Cablestream
TM
QAMReceiver Block Diagram
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