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參數資料
| 型號： | CWB5341CY |
| 廠商： | CALOGIC LLC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Dual Monolithic CMOS/DMOS T Configuration Analog Switch |
| 中文描述： | DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO14 |
| 封裝： | PLASTIC, SO-14 |
| 文件頁數： | 1/3頁 |
| 文件大小： | 36K |
| 代理商： | CWB5341CY |
Dual Monoithc CMOS/DMOS
T ConfigurationAnalog Swtch
CWB5341
FEATURES
Ultra High OFF Isolation . . . . . . . . . . . . > 80dB @ 10MHz
Low Channel-to-Channel Cross Talk. . . > 80dB @ 10MHz
TTL Compatible Inputs
Low ON Resistance. . . . . . . . . . . . . . . . . . . . . < 100ohms
Wide Bandwidth. . . . . . . . . . . . . . . . . . . -1.0dB @ 50MHz
APPLICATIONS
RF and Video Switching
High Frequency Cross Points
Video Routing
Data Acquisition
DESCRIPTION
The CWB5341 is a Dual Monolithic Analog Switch. Designed
utilizing "T" switching techniques this device gives
exceptionally low crosstalk and very high OFF isolation. The
CWB5341 is built on the Calogic proprietary CMOS/DMOS
process to achieve TTL compatibility with ultra low
capacitance and superior switching performance.
ORDERING INFORMATION
Part
CWB5341CP Plastic 14-Pin Dip
CWB5341CY Plastic SO-14 Surface Mount 0 to +85
o
C
XCWB5341
Sorted Chips in Carriers
Package
Temperature Range
0 to +85
o
C
0 to +85
o
C
C ORPORATION
PIN CONFIGURATION
FUNCTION DIAGRAM
All devices contain diodes to protect inputs against damage due to
high static voltages or electric fields; however, it is advised that
precautions be taken not to exceed the maximum recommended
input voltages. All unused inputs must be connected to an
appropriate logic level (either V
cc
or GND).
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V+
COMMON 1
D1
GND
D2
V-
COMMON 2
S1
COMMON 1
IN1
N/C
IN2
S2
N/C
CWB5341CP
S1
IN1
S2
IN2
D1
COMMON 1
C0MM0N 2
GND
D2
Two SPST 'T' Switches per Package.
Switches shown in Logic '0' Input Position.
Compensation Networks can be connected to Common 1 and Common 2.
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V+
COMMON 1
D1
GND
D2
V-
COMMON 2
S1
COMMON 1
IN1
N/C
IN2
S2
N/C
CWB5341CY
CWB
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