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參數資料
| 型號： | CXD9450-25 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip FaxEngine Product Family |
| 中文描述： | 單芯片FaxEngine產品系列 |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 114K |
| 代理商： | CXD9450-25 |
Data Sheet
Conexant
Doc. No. 100544C
September 8, 2000
Single-Chip FaxEngine Product Family
Single-Chip FaxEngine (CXD9450)
and Integrated Analog Device (CX20415)
The Conexant Single-Chip FaxEngine product family consists of the Single-Chip
FaxEngine (CXD9450) that contains an embedded modem Digital Signal Processor
(DSP), and a separate Integrated Analog (IA) device (20415).
This device set, along with the supporting firmware and evaluation system,
comprises a complete facsimile machine—needing only power supply, scanner, and
printer mechanism components to complete the machine. A system-level block
diagram is shown in
Figure 1
.
Integrated Controller
The integrated controller (SCC) provides the majority of the electronics necessary to
build a thermal or thermal transfer facsimile machine integrated into a one-chip
solution. The controller performs primary facsimile control/monitoring and
compression/decompression functions, and interfaces with fax machine
components such as a scanner, printer, motor, and operator control panel. The
MC24 embedded processor provides an external 16-MB direct memory access
capability. An integrated Pipeline ADC, combined with Conexant's Image
Processing Scheme, provides state of the art image processing performance on text
and gray scale images.
Embedded Modem DSP
The embedded modem DSP supports V.29 and V.27 ter facsimile transmission and
reception, in addition to all basic HDLC functions and T.30 requirements. The
modem allows all line connections and single or dual tone generation and detection.
Optional features such as V.17, voice compression/decompression for Digital
Telephone Answering Machine (DTAM), and duplex speakerphone are also
available.
Figure 1. Single-Chip FaxEngine System Level Block Diagram
Line IA
SRAM
1 MB
CCD or CIS
Scanner
ROM
2 MB
DRAM
8 MB
Thermal Printer or
Thermal Transfer
SCC
DSP
Operator
Panel
Single-Chip FaxEngine (CXD9450)
Telephone
Line
Control Bus
Data Bus
Address Bus
8
24
Local
Handset
20
20
11
8
24
NOR
FLASH
2 MB
20
Secondary
Line IA
Speaker
Phone
DAA
Plain Paper
Inkjet Printer
(Optional)
Features
Microprocessor and
Bus Interface
MC24 Central Processing Unit
Up to 10 MHz CPU clock speed
Memory efficient input/output bit
manipulation
24-bit internal address bus,
8-bit data bus
External Bus
Address, data, control, status,
and decoded chip select signals
support connection to external
ROM, SRAM, DRAM and
operator panel
24-bit external address bus
8-bit data bus
Chip selects
ROMCSn for ROM support
CS0n for SRAM
CS1n-CS5n for external I/O
FCSn for FLASH memory
support
LCDCS for LCD support
DRAM Controller
DRAM is refreshed in Sleep and
Stand-by modes
Up to 8 MB supported in two
blocks
Organizations supported:
4 or 8-bit
Single and page mode access
support
Flash memory support
NAND and NOR-type support
Serial NAND support
NOR-type memory up to 2 MB
DMA Controller
Six dedicated internal DMA
channels for scanner, thermal
printer, and T.4/T.6 access of
internal and/or external
memory.
DMA Channel 2 can be
reprogrammed for external
access to plain paper inkjet
printing
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