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參數資料
| 型號： | CY2304SC-1 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 109K |
| 代理商： | CY2304SC-1 |
3.3V Zero Delay Buffer
CY2304
Cypress Semiconductor Corporation
Document #: 38-07247 Rev. *C
3901 North First Street
San Jose
CA 95134
Revised December 7, 2002
408-943-2600
Features
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
Multiple configurations – see “Available Configura-
tions” table
Multiple low-skew outputs
—Output-output skew less than 200 ps
—Device-device skew less than 500 ps
10-MHz to 133-MHz operating range
Low jitter, less than 200 ps cycle-cycle
Space-saving 8-pin 150-mil SOIC package
3.3V operation
Industrial temperature available
Functional Description
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
25
μ
A of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the
“
Available Configurations
”
table. The CY2304
–
1
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY2304
–
2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin.
PLL
CLKA1
CLKA2
CLKB1
REF
CLKB2
/2
Extra Divider (-2)
Logic Block Diagram
1
2
3
4
5
8
7
6
REF
CLKA1
CLKA2
GND
V
DD
CLKB2
FBK
CLKB1
Top View
8-pin SOIC
Pin Configuration
FBK
Available Configurations
Device
FBK from
Bank A Frequency Bank B Frequency
CY2304-1
Bank A or B
Reference
Reference
CY2304-2
Bank A
Reference
Reference/2
CY2304-2
Bank B
2
×
Reference
Reference
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| CY2304SI-2 | 3.3V Zero Delay Buffer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY2304SC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V Zero Delay Buffer |
| CY2304SC-2 | 功能描述:時鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2304SC-2T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 8-Pin SOIC T/R |
| CY2304SI-1 | 功能描述:時鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2304SI-1T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 8-Pin SOIC T/R |
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