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參數(shù)資料
| 型號： | CY2305C-1 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Zero Delay Buffers |
| 中文描述： | 零延遲緩沖器 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 134K |
| 代理商： | CY2305C-1 |
Errata Revision: [**]
CY2305C
CY2309C
May 10, 2007
Errata Document for CY2305C, CY2309C Zero Delay Buffers
Cypress Semiconductor Corporation
198 Champion Court
San Jose
,
CA 95134
408.943.2600
Document Number: 001-15585 Rev. **
Revised May 10, 2007
This document describes the errata for the Zero Delay Clock Buffers, CY2305C and CY2309C. Details include errata
trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document
to the device’s data sheet for a complete functional description.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Zero Delay Buffer Qualification Status
In Production
Zero Delay Buffer Errata Summary
The following table defines the errata applicability to available Zero Delay Buffer family devices.
Note
Errata titles are hyperlinked. Click on the table item entry to jump to its description.
1. Possible increased power down current
PROBLEM DEFINITION
When the device is in the power down state, an unbonded pad on the die is allowed to float. Because of this,
power down current may exceed the data sheet limit.
While high current draw is theoretically possible any time during power down, it has only been observed as a
transient occurrence shortly after the device enters power down. Steady-state current has always been ob-
served to be within data sheet limits.
PARAMETERS AFFECTED
TRIGGER CONDITION(S)
None.
Part Number
CY2305C-1
CY2305C-1H
CY2309C-1
CY2309C-1H
Temperature Grades
all
all
all
all
Packages
all
all
all
all
Items
Part Numbers
All
Fix Status
[1] Possible increased power down current
Will be corrected in the next silicon revision. The
errata is forecast to be corrected for all devices
dated October 2007 and later.
Parameter
IDD (PD Mode)
Temperature Range
Commercial
Industrial
Data Sheet Maximum
12 μA
25 μA
Actual Maximum
3.5 mA
3.5 mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2305C-1H | Zero Delay Buffers |
| CY2309C | Zero Delay Buffers |
| CY2309C-1 | Zero Delay Buffers |
| CY2309C-1H | Zero Delay Buffers |
| CY2308-1 | 3.3V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2305C-1H | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Zero Delay Buffers |
| CY2305CSX-1 | 制造商:Cypress Semiconductor 功能描述: |
| CY2305CSXA-1 | 功能描述:時鐘緩沖器 3.3V Zero Delay Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2305CSXA-1H | 功能描述:時鐘緩沖器 3.3V Zero Delay Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2305CSXA-1HT | 功能描述:鎖相環(huán) - PLL 3. 3V ZDB Internal Feedck RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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