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參數(shù)資料
| 型號： | CY2305SC-1HT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW-COST 3.3V ZERO DELAY BUFFER |
| 中文描述： | 2305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 200K |
| 代理商： | CY2305SC-1HT |
Low-cost 3.3V Zero Delay Buffer
CY2305
CY2309
Cypress Semiconductor Corporation
Document #: 38-07140 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 14, 2002
Features
10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
Zero input-output propagation delay
Multiple low-skew outputs
—Output-output skew less than 250 ps
—Device-device skew less than 700 ps
—One input drives five outputs (CY2305)
—One input drives nine outputs, grouped as 4 + 4 + 1
(CY2309)
Less than 200 ps cycle-cycle jitter, compatible with
Pentium
-based systems
Test Mode to bypass phase-locked loop (PLL) (CY2309
only [see “Select Input Decoding” on page 2])
Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil
SOIC package (CY2305)
3.3V operation
Industrial temperature available
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the
“
Select Input
Decoding
”
table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0
μ
A of current draw for commercial temper-
ature devices and 25.0
μ
A for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter. The input
to output propagation delay on both devices is guaranteed to
be less than 350 ps, and the output to output skew is
guaranteed to be less than 250 ps.
The CY2305/CY2309 is available in two/three different config-
urations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
SOIC/TSSOP
Top View
Pin Configuration
2309-1
2309-2
1
2
3
4
5
8
7
6
REF
CLK2
CLK1
GND
V
DD
CLK3
CLKOUT
CLK4
SOIC
Top View
2309-3
PLL
MUX
Select Input
Decoding
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLKOUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2305SC-1T | LOW-COST 3.3V ZERO DELAY BUFFER |
| CY2309SI-1HT | LOW-COST 3.3V ZERO DELAY BUFFER |
| CY2309SI-1T | LOW-COST 3.3V ZERO DELAY BUFFER |
| CY2309 | LOW-COST 3.3V ZERO DELAY BUFFER |
| CY2309ZC-1HT | RF Coaxial Connector Adapter; Body Plating:Passivated Steel; Body Style:Straight Adapter, Plug-Plug RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2305SC-1T | 制造商:Cypress Semiconductor 功能描述:3.3 V ZERO DELAY BUFFER - Tape and Reel 制造商:Cypress Semiconductor 功能描述:3.3V ZDB WITH INTERNAL FEEDBACK-8 PIN 制造商:Rochester Electronics LLC 功能描述:3.3 V ZERO DELAY BUFFER - Bulk |
| CY2305SI-1 | 功能描述:鎖相環(huán) - PLL 3.3VZDB IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2305SI-1H | 功能描述:鎖相環(huán) - PLL 3.3VZDB COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2305SI-1HT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 8-Pin SOIC T/R 制造商:Cypress Semiconductor 功能描述:3.3 V ZERO DELAY BUFFER - Tape and Reel |
| CY2305SI-1T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 10MHz to 133MHz 8-Pin SOIC T/R |
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