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參數資料
型號: CY2310BNZ
英文描述: Clocks and Buffers
中文描述: 時鐘和緩沖器
文件頁數: 1/6頁
文件大小: 75K
代理商: CY2310BNZ
3.3V SDRAM Buffer for Mobile PCs
with Four SO-DIMMs
CY2310BNZ
Cypress Semiconductor Corporation
Document #: 38-07260 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 28, 2003
Features
One input to 10 output buffer/driver
Supports up to four SDRAM SO-DIMMs
Two additional outputs for feedback
SMBus interface for output control
Low skew outputs
Up to 100 MHz operation
Multiple V
DD
and V
SS
pins for noise reduction
Dedicated OE pin for testing
Space-saving 28-pin SSOP package
3.3V operation
Description
The CY2310BNZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has ten
outputs, eight of which can be used to drive up to four SDRAM
SO-DIMMs, and the remaining can be used for external
feedback to a PLL. The device operates at 3.3V and outputs
can run up to 100 MHz, thus making it compatible with
Pentium II
processors. The CY2310BNZ can be used in
conjunction with the CY2281 or similar clock synthesizer for a
full Pentium II motherboard solution.
The CY2310BNZ also includes an SMBus interface that can
enable or disable each output clock. On power-up, all output
clocks are enabled. A separate Output Enable pin facilitates
testing on ATE.
Block Diagram
SMBus
Decoding
BUF_IN
SDATA
SCLOCK
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
1
2
3
4
5
6
7
V
SDRAM7
SDRAM6
V
SS
V
DD
SDRAM5
SDRAM4
V
SS
OE
V
SDRAM9
V
SS
V
SCLOCK
28-pin SSOP
Top View
Pin Configuration
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
SDRAM0
SDRAM1
V
SS
V
SDRAM2
SDRAM3
V
SS
BUF_IN
V
DD
SDRAM8
V
SS
V
DDIIC
SDATA
OE
C
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