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參數(shù)資料
| 型號(hào)： | CY23FS04ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Failsafe 2.5V/ 3.3V Zero Delay Buffer |
| 中文描述： | 170 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, MO-153, TSSOP-16 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 216K |
| 代理商： | CY23FS04ZI |
Failsafe 2.5V/ 3.3V Zero Delay Buffer
CY23FS04
Cypress Semiconductor Corporation
Document #: 38-07304 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised October 12, 2004
Features
Internal DCXO for continuous glitch-free operation
Zero input-output propagation delay
Low-jitter (< 35 ps RMS) outputs
Low Output-to-Output skew (< 200 ps)
4.17 MHz–170 MHz reference input
Supports industry standard input crystals
170 MHz outputs
5V-tolerant inputs
Phase-locked loop (PLL) Bypass Mode
Dual Reference Inputs
16-pin TSSOP
2.5V or 3.3V output power supplies
3.3V core power supply
Industrial temperature available
Functional Description
The CY23FS04 is a FailSafe
zero delay buffer with two
reference clock inputs and four phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
The continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS04 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by two select lines:
S[2:1], please see
Table 1
. Output power supply, VDD can be
connected to either 2.5V or 3.3V. VDDC is the power supply
pin for internal circuits and must be connected to 3.3V.
Block Diagram
Pin Configuration
CLKA[1:2]
CLKB[1:2]
DCXO
Decoder
2
Failsafe
TM
Block
PLL
XIN XOUT
2
2
REF2
FBK
S[2:1]
FAIL# /SAFE
REF1
REFSEL
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C
16 pin TSSOP
REF1
REF2
CLKB1
CLKB2
VSS
VDDC
XIN
S2
REFSEL
FBK
CLKA1
CLKA2
S1
VDD
FAIL#/SAFE
XOUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY23FS04ZIT | Failsafe 2.5V/ 3.3V Zero Delay Buffer |
| CY23S02 | Spread Aware, Frequency Multiplier and Zero Delay Buffer |
| CY23S02-01SC | Spread Aware, Frequency Multiplier and Zero Delay Buffer |
| CY23S02-01SI | Spread Aware, Frequency Multiplier and Zero Delay Buffer |
| CY23S08ZC-1H | 3.3V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23FS04ZIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer |
| CY23FS04ZXC | 功能描述:鎖相環(huán) - PLL 2.5V 3.3V Zero Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23FS04ZXC-2 | 功能描述:鎖相環(huán) - PLL 3.3V 170MHz COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23FS04ZXC-2T | 功能描述:鎖相環(huán) - PLL 3.3V 170MHz COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23FS04ZXC-5 | 功能描述:鎖相環(huán) - PLL CY23FS04ZXC-5 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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