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參數(shù)資料
| 型號： | CY24142ZXC-01T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | MediaClock Multimedia Clock Generator |
| 中文描述： | 54 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, LEAD FREE, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 129K |
| 代理商： | CY24142ZXC-01T |
MediaClock
Multimedia Clock Generator
CY24142
Cypress Semiconductor Corporation
Document #: 38-07532 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 19, 2005
Features
Integrated phase-locked loop (PLL)
Low-jitter, high-accuracy outputs
3.3V operation
Benefits
Integrated high-performance PLL eliminates the need for
— external loop filter components
Meets critical timing requirements in complex system
designs
Enables application compatibility
Output Enable Options
[1]
Logic Block Diagram
Pin Configuration
XIN
XOUT
MOUTPUT
DIAND
PLL
OSC.
CLK1 13.5 MHz
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
CLK2 54 MHz
CLK3 18.432 MHz
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
NC
OE2
CLK2
XIN
VDD
AVDD
XOUT
AVSS
CLK4
CLK3
VDDL
NC
CLK1
OE1
CLK4 18.432 MHz
VDD
VSSL
CY24142
OE2
OE1
Frequency Table
Part Number
CY24142-01
Outputs
4
Input Frequency
18.432
Output Frequency Range
13.5 MHz, 54 MHz, 2
x
18.432 MHz
OE2
0
0
1
1
OE1
0
1
0
1
CLK1
13.5
13.5
13.5
13.5
CLK2
OFF
54
OFF
54
CLK3
OFF
18.432
OFF
18.432
CLK4
OFF
OFF
18.432
18.432
Unit
MHz
MHz
MHz
MHz
Note:
1. Output driven LOW when “OFF.”
相關PDF資料 |
PDF描述 |
|---|---|
| CY24142-01 | MediaClock Multimedia Clock Generator |
| CY24142ZC-01 | MediaClock Multimedia Clock Generator |
| CY24142ZC-01T | MediaClock Multimedia Clock Generator |
| CY241V08A-05 | MPEG Clock Generator with VCXO |
| CY241V08A-06 | MPEG Clock Generator with VCXO |
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| CY241V08-41 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY241V08A-01 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MPEG Clock Generator with VCXO |
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