
Programmable Spread Spectrum
Clock Generator for EMI Reduction
CY25000
Cypress Semiconductor Corporation
Document #: 38-07424 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 26, 2003
Features
Wide operating output (SSCLK) frequency range
— 3–200 MHz
Programmable spread spectrum with nominal 30-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
Input frequency range
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
Integrated phase-locked loop (PLL)
Programmable crystal load capacitor tuning array
Low cycle-to-cycle Jitter
3.3V operation
Spread spectrum On/Off function
Power-down or Output Enable function
Benefits
Services most PC peripherals, networking, and consumer
applications.
Provides wide range of spread percentages for maximum
EMI reduction, to meet regulatory agency Electro Magnetic
Compliance (EMC) requirements. Reduces development
and manufacturing costs and time-to-market.
Eliminates the need for expensive and difficult to use higher
order crystals.
Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
Enables fine-tuning of output clock frequency by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
Suitable for most PC, consumer, and networking applica-
tions
Application compatibility in standard and low-power
systems.
Provides ability to enable or disable spread spectrum with
an external pin.
Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
XIN/CLKIN
Dividers
and
PLL
OSC.
REFCLK
VSS
SSCLK
VDD
SSON
XOUT
MUX
Output
with
Modulation Control
Programmable Configuration
C
XIN
1
8
3
7
6
5
2
4
C
XOUT
8-pin SOIC
CY25000
Pin Configuration
1
2
3
4
XOUT
SSCLK
VSS
SSON
REFCLK
5
6
7
8
VDD
XIN/CLKIN
PD#/OE
PD#/OE