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參數(shù)資料
| 型號： | CY26049-1 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 51K |
| 代理商： | CY26049-1 |
ADVANCE
INFORMATION
FailSafe PacketClock
Global Communications Clock Generator
CY26049-1
Cypress Semiconductor Corporation
Document #: 38-07488 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 8, 2003
Features
Fully integrated phase-locked loop (PLL)
FailSafe output
PLL driven by a crystal oscillator that is phase-aligned
with external reference
Two 6.312-MHz outputs from 8-kHz input
Low-jitter, high-accuracy outputs
3.3V ± 5% operation
16-lead TSSOP
Benefits
Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
DCXO maintains continuous operation should the input
reference clock fail
Glitch-free transition simplifies system design
Works with commonly available, low-cost 18.432-MHz
crystal
Zero-ppm error for all output frequencies
Compatible across industry standard design platforms
Industry standard package with 6.4 × 5.0 mm
2
footprint and
a height profile of just 1.1 mm
Logic Block Diagram
CLKB
6.312MHz
XIN
XOUT
ICLK
CLKA
6.312MHz
SAFE
ICLK detected
input reference clock
(typical 8kHz)
external pullable crystal
(18.432MHz)
DIGITAL
CONTROLED
CRYSTAL
OSCILLATOR
FAILSAFE
TM
CONTROL
PHASE
LOCKED
LOOP
OUTPUT
DIVIDERS
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PDF描述 |
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| CY26049-3 | Clocks and Buffers |
| CY26049-36 | Clocks and Buffers |
| CY26049-5 | Clocks and Buffers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY26049-22 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FailSafe⑩ PacketClock⑩ Global Communications Clock Generator |
| CY26049-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY26049-36 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY26049-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY26049KZXI-36 | 制造商:Cypress Semiconductor 功能描述: |
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