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參數(shù)資料
| 型號： | CY26118 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 50K |
| 代理商： | CY26118 |
One-PLL General Purpose
Clock Generator
CY26111
Cypress Semiconductor Corporation
Document #: 38-07095 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Benefits
Integrated phase-locked loop
Low skew, low jitter, high-accuracy outputs
3.3V Operation with 2.5V Output Option
16-TSSOP
Internal PLL with up to 333 MHz internal operation
Meets critical timing requirements in complex system designs
Enables application compatibility
Industry standard package saves on board space
Part Number
CY26111
Outputs
4
Input Frequency
25 MHz
Output Frequency Range
3 x 25 MHz, 1 x 125 MHz
Output
LCLK1
LCLK2
LCLK3
CLK4
Pin
7
8
9
15
Default Frequency
25
25
25
125
Unit
MHz
MHz
MHz
MHz
Logic Block Diagram
XIN
XOUT
LCLK1 25 MHz
OUTPUT
MULTIPLEXER
DIAND
PLL
OSC.
LCLK3 25 MHz
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
OE
LCLK2 25 MHz
CLK4 125 MHz
VSSL
VDD
16-pin TSSOP
CY26111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
NC
LCLK3
LCLK1
LCLK2
XIN
VDD
AVDD
XOUT
OE
AVSS
CLK4
NC
VDDL
N/C
Pin Configurations
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