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參數(shù)資料
| 型號(hào)： | CY26503 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 161K |
| 代理商： | CY26503 |
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533-MHz Direct Rambus Clock Generator
CY26501/CY26502
Cypress Semiconductor Corporation
Document #: 38-07356 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
Features
Differential clock source for Direct Rambus
memory
subsystem for up to 1066-MHz data transfer rate
Provide synchronization flexibility: the Rambus
Chan-
nel can optionally be synchronous to an external sys-
tem or processor clock
Power managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
Cycle to Cycle Jitter below 50 ps
Low-power CMOS design packaged in a 24-pin, 150-mil
SSOP package
Support up to 533MHz for Commercial temperature and
400 MHz for Industrial temperature.
Overview
The Cypress CY26501 and CY26502 provide the differential
clock signals for a Direct Rambus memory subsystem. It in-
cludes signals to synchronize the Direct Rambus Channel
clock to an external system clock but can also be used in sys-
tems that do not require synchronization of the Rambus clock.
Key Specifications
Supply Voltage: ..................................... V
DD
= 3.3V±0.165V
Operating Temperature(Commercial): ............. 0
°
C to +70
°
C
Operating Temperature(Industrial): .............. -40
°
C to +85
°
C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:.........................................V
DD
+0.5V
Maximum Input Frequency:.....................................100 MHz
Output Duty Cycle: .................................. 40/60% worst case
Output Type:........................... Rambus signaling level (RSL)
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.
Intel is a registered trademark of Intel Corporation.
Block Diagram
Pin Configuration
PLL
Phase
Alignment
PCLKM
MULT0:1
REFCLK
SYNCLKN
Output
Logic
Logic
Test
STOPB
S0:1
CLK
CLKB
S0
S1
VDD
GND
CLK
NC
CLKB
GND
VDD
MULT0
MULT1
GND
24
23
22
21
20
19
18
17
16
15
14
13
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
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