- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380125 > CY29772AIT (CYPRESS SEMICONDUCTOR CORP) 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer PDF資料下載
參數(shù)資料
| 型號： | CY29772AIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-52 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 92K |
| 代理商： | CY29772AIT |
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
CY29772
Cypress Semiconductor Corporation
Document #: 38-07572 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 27, 2003
Features
Output frequency range: 8.33 MHz to 200 MHz
Input frequency range: 6.25 MHz to 125 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2% max Output duty cycle variation
12 clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: crystal or LVCMOS
300ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread Aware
Output enable/disable
Pin-compatible with MPC9772 and MPC972
Industrial temperature range: –40°C to +85°C
52-pin 1.0-mm TQFP package
Description
The CY29772 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed
clock-distribution applications.
The CY29772 features one on-chip crystal oscillator and two
LVCMOS reference clock inputs and provides 12 outputs parti-
tioned in three banks of four outputs each. Each bank divides
the VCO output per SEL(A:C) settings, see
Functional Table
.
These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1,
3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50
series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces,
giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider, see
Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
AVSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
AVDD
F
S
V
Q
V
Q
S
S
Q
V
Q
V
I
S
S
S
S
Q
V
Q
V
Q
V
Q
V
V
VSS
QB0
VDDQB
QB1
VSS
QB2
VDDQB
QB3
FB_IN
VSS
FB_OUT
VDD
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29772
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29773 | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| CY29773AI | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| CY29773AIT | 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| CY29940 | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
| CY29940AC | 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29772AXI | 功能描述:鎖相環(huán) - PLL 2.5V or 3.3V 200MHz Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29772AXIT | 功能描述:鎖相環(huán) - PLL 2.5V or 3.3V 200MHz Delay Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY29773 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
| CY29773AI | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Buffer Single 52-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2.5V OR 3.3V,200MHZ,3:12 LVPECL/LVCMOS INPUTS ZDB - Bulk |
| CY29773AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。