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參數資料
| 型號： | CY29FCT818TSOIC |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Diagnostic Scan Register |
| 中文描述： | 診斷掃描寄存器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 93K |
| 代理商： | CY29FCT818TSOIC |
Diagnostic Scan Register
CY29FCT818T
SCCS012 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function,pinoutanddrivecompatiblewithFCT,FLogic
and AM29818
FCT-C speed at 6.0 ns max. (Com’l),
FCT-A speed at 12.0 ns max. (Mil)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Sink current
64 mA (Com’l),
20 mA (Mil)
Source current
32 mA (Com’l),
3 mA (Mil)
8-Bit pipeline and shadow register
ESD > 2000V
Functional Description
The FCT818T contains a high-speed 8-bit general-purpose
data pipeline register and a high-speed 8-bit shadow register.
The general-purpose register can be used in an 8-bit wide
data path for a normal system application. The shadow regis-
ter is designed for applications, such as diagnostics in sequen-
tial circuits, where it is desirable to load known data at a spe-
cific location in the circuit and to read the data at that location.
The shadow registers can load data from the output of the
FCT818T, and can be used as a right-shift register with
bit-serial input SDI and output SDO, using DCLK. The data
register input is multiplexed to enable loading from the shadow
register or from the data input pins using PCLK. Note that data
can be loaded simultaneously from the shadow register to the
pipeline register, and from the pipeline register to the shadow
register provided set-up and hold time requirements are
satisfied with respect to the two independent clock inputs.
In a typical application, the general-purpose register in the
FCT818T replaces an 8-bit data register in the normal data
path of a system. The shadow register is placed in an auxiliary
bit-serial loop which is used for diagnostics. During diagnostic
operation, data is shifted serially into the shadow register, then
transferred to the general purpose register to load a known
value into the data path. To read the contents at that point in
the data path, the data is transferred from the data register into
the shadow register, then shifted serially in the auxiliary
diagnostic loop to make it accessible to the diagnostics
controller. This data is then compared with the expected value
to diagnose faulty operation of the sequential circuit.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
OE
DCLK
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SDI
GND
D
0
V
CC
MODE
Y
0
Y
1
Y
2
SDO
Y
3
Y
4
Y
5
Y
6
Y
7
15
Top View
28
27
26
4
3
2
1
2021 222324
19
D
D
Y2
Y5
25
Y1
Y
7
D
7
SDI
GND
NC
PCLK
D
0
DCLK
OE
NC
V
cc
N
N
MODE
Y
0
Y4
D
LCC
Top View
Y3
5
6
7
8
9
10
11
D
D
12
13
14
15
16
17
18
D
PCLK
Y6
SDO
DIP, SOIC, QSOP
8-BIT
SHADOW
REGISTER
CLK
D
Q
MUX
8-BIT
PIPELINE
REGISTER
OE
PCLK
MODE
DCLK
SDI
SDO
D
0
D
7
P
0
P
7
Y
0
Y
7
8
8
8
8
S
0
S
7
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