- 您現在的位置：買賣IC網 > PDF目錄380127 > CY2DP818ZC (CYPRESS SEMICONDUCTOR CORP) CRIMP SHELLS DB9 MALE PDF資料下載
參數資料
| 型號： | CY2DP818ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CRIMP SHELLS DB9 MALE |
| 中文描述： | 2DP SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO38 |
| 封裝： | 4.40 MM, TSSOP-38 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 92K |
| 代理商： | CY2DP818ZC |
1:8 Clock Fanout Buffer
ComLink Series
CY2DP818
Cypress Semiconductor Corporation
Document #: 38-07061 Rev. *A
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised July 9, 2002
Features
Low-voltage operation V
DD
= 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical
(tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at
350 MHz
–
700 Mbps
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry
’
s fastest logic.
The Cypress CY2DP818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the Inconfig pin for single ended
or differential input.
Block Diagram
Pin Configuration
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
38-pin TSSOP
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
VDD
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4B
GND
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
VDD
VDD
VDD
VDD
VDD
InConfig
INPUT A
INPUT B
GND
GND
C
相關PDF資料 |
PDF描述 |
|---|---|
| CY2DP818ZCT | Computers; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| CY2DP818ZI | COMPUTER ACCESSORY |
| CY2DP818ZIT | CRIMP SHELLS DB9 FEMALE |
| CY2DP818 | 1:8 Clock Fanout Buffer(1:8時鐘輸出緩沖器) |
| CY2V995 | S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY2DP818ZC-2 | 制造商:Rochester Electronics LLC 功能描述:3.3V,450MHZ 1:8 DIFFERENTIAL TO LVPECL BUFFER - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY2DP818ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
| CY2DP818ZCT | 制造商:Cypress Semiconductor 功能描述: |
| CY2DP818ZI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY2DP818ZI-2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。