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| 型號(hào)： | CY3138R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大小： | 63K |
| 代理商： | CY3138R62 |
Warp
Enterprise VHDL CPLD Software
CY3130
Cypress Semiconductor Corporation
Document #: 38-03050 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 18, 2003
Features
VHDL (IEEE 1076 and 1164) high-level language
compilers with the following features
—Designs are portable across multiple devices
and/or EDA environments
—Facilitates the use of industry-standard simulation
and synthesis tools for board- and system-level de-
sign
—Support for functions and libraries facilitating
modular design methodology
—Support for enumerated types, operator overload-
ing, For... Generate statements and Integers
Several design entry methods support high-level and
low-level design descriptions
—Graphical HDL Block Diagram editor with a library of
blocks and a text-to-block conversion utility from
Aldec
—Aldec Active-HDL FSM graphical Finite State
Machine editor
—Behavioral VHDL (IF...THEN...ELSE; CASE...)
—Boolean
—Structural VHDL
—Designs can include multiple entry methods (but
only one HDL) in a single design.
Language Assistant library of VHDL templates
Flow Manager Interface to keep track of complex
projects
UltraGen Synthesis and Fitting Technology
—Infers “modules” such as adders, comparators, etc.,
from behavioral descriptions and replaces them with
circuits pre-optimized for the target device
—User-selectable speed and/or area optimization on a
block-by-block basis
—Perfectly integrated synthesis and fitting
—Automatic selection of optimal flip-flop type
(D type/T type)
—Automatic pin assignment
Ability to specify timing constraints for all of the
Delta39K and PSI devices
Support for all Cypress Programmable Logic Devices
—Programmable Serial Interface (PSI)
—Delta39K CPLDs
—Ultra37000 CPLDs
—F
LASH
370i CPLDs
—MAX340 CPLDs
—Industry standard PLDs (16V8, 20V8, 22V10)
VHDL or Verilog timing model output for use with
third-party simulators
Timing simulation provided by Active-HDL Sim
Release 4.1 from Aldec
—Graphical waveform simulator
—Graphical entry and modification of all waveforms
—Ability to compare waveforms and highlight differ-
ences before and after a design change
—Ability to probe internal nodes
—Display of inputs, outputs, and high-impedance (Z)
signals in different colors
—Automatic clock and pulse creation
—Support for buses
—Unlimited simulation time
Architecture Explorer and Dynamic Timing Simulator
for PSI and Delta39K devices:
—Graphical representation of exactly how your design
will be implemented on your specific target device
—Zoom from the device level down to the macrocell
level
—Determine the timing for any path and view that path
on a graphical representation of the chip
Static Timing Report for all devices
Source-Level Behavioral Simulation and Debugger
from Aldec
Testbench Generation
C3ISR Programming Cable
Delta39K\Ultra37000 prototype board with a CY37256V
160-pin TQFP device and a CY39100V 208-pin PQFP
device
On-line documentation and help
Functional Description
Warp
Enterprise is an integration of the
Warp
Profes-
sional
CPLD Development package with additional sophis-
ticated EDA software features from Aldec. In addition to
accepting IEEE 1076/1164 VHDL text and graphical finite state
machines for design entry,
Warp
Enterprise VHDL provides a
graphical HDL block diagram editor with a library of graphical
HDL blocks pre-optimized for Cypress devices. Plus, it
provides a utility to convert HDL text into graphical HDL blocks.
Warp
Enterprise synthesizes and optimizes the entered
design, and outputs a JEDEC or Intel
hex file for the desired
PLD or CPLD (see
Figure 1
). For simulation,
Warp
Enterprise
provides a timing simulator, a source-level behavioral
simulator, as well as VHDL and Verilog timing models for use
with third party simulators.
Warp
Enterprise also provides the
designer with important productivity tools such as a testbench
generation wizard and the Architecture Explorer graphical
analysis tool.
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