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參數資料
| 型號： | CY3672ADP000 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | One-PLL General Purpose Flash Programmable Clock Generator |
| 中文描述： | 一個通用閃存鎖相環可編程時鐘發生器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 156K |
| 代理商： | CY3672ADP000 |
One-PLL General Purpose
Flash Programmable Clock Generator
CY22050
Cypress Semiconductor Corporation
Document #: 38-07006 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 29, 2005
Features
Benefits
Integrated phase-locked loop (PLL)
Internal PLL to generate six outputs up to 200 MHz. Able to generate
custom frequencies from an external reference crystal or a driven source.
Performance guaranteed for applications that require an extended temper-
ature range.
Reprogrammable technology allows easy customization, quick turnaround
on design changes and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for upgrading
existing designs.
In-house programming of samples and prototype quantities is available
using the CY3672 FTG Development Kit. Production quantities are
available through Cypress’s value-added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems, and
others.
High performance suited for commercial, industrial, networking, telecomm
and other general-purpose applications.
Application compatibility in standard and low-power systems.
Industry standard packaging saves on board space.
Commercial and Industrial operation
Flash-programmable
Field-programmable
Low-skew, low-jitter, high-accuracy outputs
3.3V operation with 2.5V output option
16-lead TSSOP
Part Number
CY22050FC
Outputs
6
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
Output Frequency Range
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Specifications
Field-programmable
commercial temperature
Field-programmable
industrial temperature
CY22050FI
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
OE
LCLK3
LCLK1
XIN
VDD
AVDD
XOUT
PWRDWN
AVSS
LCLK2
CLK6
CLK5
VDDL
LCLK4
Pin Configuration
XIN
XOUT
Divider
Bank 1
PLL
OSC.
LCLK3
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
LCLK2
LCLK4
CLK5
CLK6
VSSL
VDD
Divider
Output
Select
OE
PWRDWN
LCLK1
Logic Block Diagram
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