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| 型號： | CY37256VP160-200UXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | BATTERY SEALED LEAD ACID 6V 12AH |
| 中文描述： | 為5V，3.3V，ISRTM高性能的CPLD |
| 文件頁數(shù)： | 1/64頁 |
| 文件大小： | 1798K |
| 代理商： | CY37256VP160-200UXC |
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5V, 3.3V, ISR High-Performance CPLDs
Ultra37000 CPLD Family
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-03007 Rev. *D
Revised October 25, 2004
Features
In-System Reprogrammable (ISR) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
3.3V and 5V versions
PCI-compatible[1]
Programmable bus-hold capabilities on all I/Os
Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
— Product term sharing among local macrocells
Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
Consistent package/pinout offering across all densities
— Simplifies design migration
— Same pinout for 3.3V and 5.0V devices
Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
BGA, and Fine-Pitch BGA packages
— Lead(Pb)-free packages available
General Description
The Ultra37000 family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both
design and manufacturing flows, thereby reducing costs. The
ISR feature provides the ability to reconfigure the devices
without having design changes cause pinout or timing
changes. The Cypress ISR function is implemented through a
JTAG-compliant serial interface. Data is shifted in and out
through the TDI and TDO pins, respectively. Because of the
superior routability and simple timing model of the Ultra37000
devices, ISR allows users to change existing logic designs
while
simultaneously
fixing
pinout
assignments
and
maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting
the
electrical
and
timing
requirements.
The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO connections provide the
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3V the output levels
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and
are
5V-tolerant.
These
devices
allow
3.3V
ISR
programming.
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
相關PDF資料 |
PDF描述 |
|---|---|
| CY37256VP208-200UXC | BATT SEALED LEAD ACID 12V 28AH |
| CY3732VP208-200UXC | BATT SEALED LEAD ACID 6V 13AH |
| CY37384VP160-200UXC | BATTERY SLA 6V 12AH .250 TERM |
| CY37384VP208-200UXC | BATTERY SEALED LEAD ACID 12V 3AH |
| CY37384VP208-83UXC | 5V, 3.3V, ISRTM High-Performance CPLDs |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY37256VP160-66AXC | 功能描述:CPLD - 復雜可編程邏輯器件 256 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY37256VP160-66UMB | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 3.3V 160-Pin CQFP |
| CY37256VP208-100NC | 制造商:Cypress Semiconductor 功能描述: |
| CY37256VP208-100NXC | 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:Ultra37000™ 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY37256VP208-66NC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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