- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄380156 > CY39050V676-200BGC (Cypress Semiconductor Corp.) CPLDs at FPGA Densities PDF資料下載
參數(shù)資料
| 型號(hào)： | CY39050V676-200BGC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁(yè)數(shù)： | 1/86頁(yè) |
| 文件大小： | 1235K |
| 代理商： | CY39050V676-200BGC |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)
CPLDs at FPGA Densities
Carry-chain logic for fast and efficient arithmetic opera-
tions
Multiple I/O standards supported
—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
Compatible with NOBL, ZBT, and QDR SRAMs
Programmable slew rate control on each I/O pin
User-programmable Bus Hold capability on each I/O pin
Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
CompactPCI hot swap ready
Multiple package/pinout offering across all densities
—208 to 676 pins in PQFP, BGA, and FBGA packages
—Simplifies design migration across density
—Self-Boot solution in BGA and FBGA packages
In-System Reprogrammable (ISR)
—JTAG-compliant on-board programming
—Design changes do not cause pinout changes
IEEE1149.1 JTAG boundary scan
Delta39K ISR
CPLD Family
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. *H
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 1, 2003
Features
High density
—30K to 200K usable gates
—512 to 3072 macrocells
—136 to 428 maximum I/O pins
—Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
Embedded memory
—80K to 480K bits embedded SRAM
16K to 96K bits of (dual-port) channel memory
High speed – 233-MHz in-system operation
AnyVolt
interface
—3.3V, 2.5V,1.8V, and 1.5V I/O capability
Low-power operation
—0.18-mm six-layer metal SRAM-based logic process
—Full-CMOS implementation of product term array
—Standby current as low as 5mA
Simple timing model
—No penalty for using full 16 product terms/macrocell
—No delay for single product term steering or sharing
Flexible clocking
—Spread Aware PLL drives all four clock networks
Allows 0.6% spread spectrum input clocks
Several multiply, divide and phase shift options
—Four synchronous clock networks per device
—Locally generated product term clock
—Clock polarity control at each register
Development Software
Warp
—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
—Active-HDL FSM graphical finite state machine editor
—Active-HDL SIM post-synthesis timing simulator
—Architecture Explorer for detailed design analysis
—Static Timing Analyzer for critical path analysis
—Available on Windows
95/98/2000/XP and
Windows NT for $99
—Supports all Cypress programmable logic products
Delta39K ISR CPLD Family Members
Device
Typical
Gates
[1]
Macrocells
Cluster
memory
(Kbits)
Channel
memory
(Kbits)
Maximum
I/O Pins
f
(MHz)
Speed-t
Pin-to-Pin
(ns)
Standby I
CC
[2]
T
A
= 25
°
3.3/2.5V
39K30
16K – 48K
512
64
16
174
233
7.2
5 mA
39K50
23K – 72K
768
96
24
218
233
7.2
5 mA
39K100
46K – 144K
1536
192
48
302
222
7.5
10 mA
39K165
77K – 241K
2560
320
80
386
181
8.5
20 mA
39K200
92K – 288K
3072
384
96
428
181
8.5
20 mA
Notes:
1.
2.
Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
Standby I
CC
values are with PLL not utilized, no output load and stable inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY39050V676-200BGI | CPLDs at FPGA Densities |
| CY39050V676-200MBC | CPLDs at FPGA Densities |
| CY39050V676-200MBI | CPLDs at FPGA Densities |
| CY39050V676-233BBI | CPLDs at FPGA Densities |
| CY39050Z208-181BBI | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39050Z208-125BBC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BBI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BGC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z208-125BGI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39050Z388-125BBC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。