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參數(shù)資料
| 型號(hào)： | CY53120 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | Neuron Chip Network Processor(Neuron 芯片網(wǎng)絡(luò)處理器) |
| 中文描述： | Neuron芯片網(wǎng)絡(luò)處理器（神經(jīng)元芯片網(wǎng)絡(luò)處理器） |
| 文件頁(yè)數(shù)： | 1/1頁(yè) |
| 文件大小： | 41K |
| 代理商： | CY53120 |
PRELIMINARY
Neuron
Chip Network Processor
CY53120
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 6, 2000, rev. **
20
Features
Maximum clock operation of 20 MHz, over a –40 to 85
°
C
temperature range
Three 8-bit pipelined processors for concurrent pro-
cessing of application code and network packets
11-pin I/O port programmable in 34 modes for fast ap-
plication program development
Two 16-bit timer/counters for measuring and generat-
ing I/O device waveforms
5-pin communication port that supports direct connect
and network transceiver interfaces
2048 bytes of SRAM for buffering network data and stor-
ing network variables
2048 bytes of EEPROM memory for flexible storage of
application code and configuration data
10 KB of ROM for storing LonTalk
network protocol
firmware
Programmable pull-ups on IO4–IO7 and 20-mA sink cur-
rent on IO0–IO3
Unique 48-bit ID number in every device to facilitate
network installation and management
32-pin SOIC or 44-pin QFP packages
Low operating current. Sleep mode operation for re-
duced current consumption
On-chip LVD circuit to prevent non-volatile memory cor-
ruption during voltage drops
0.35-
μ
m Flash process technology
5.0V operation
Functional Description
The CY53120 is a Neuron Chip which implements a node for
the LonWorks distributed intelligent control networks. It in-
corporates, on a single chip, the necessary communication
and control functions, both in hardware and firmware, that fa-
cilitate the design of a LonWorks node.
The CY53120 is manufactured using the state-of-the-art
0.35-
μ
m Flash technology, providing to the designers the most
cost-effective Neuron Chip solution.
Services at every layer of the OSI networking reference model
are implemented in the LonTalk firmware-based protocol
stored in the 10-KB ROM. In addition, the ROM firmware also
contains preprogrammed I/O drivers, greatly simplifying appli-
cation programming. The application program is stored in the
EEPROM memory, and may be updated by downloading over
the network.
The CY53120 contains a very flexible 5-pin communication
port, that can be configured to interface to a wide variety of
media transceivers at a wide range of data rates. The most
common transceiver types are: twisted-pair, powerline, RF, IR,
fiber-optics, and coaxial.
The CY53120 Neuron Chip is fully compatible with the Motor-
ola MC143120E2 device.
Echelon, LonWorks, LonBuilder, LonTalk, NodeBuilder, and Neuron are registered trademarks of Echelon Corporation.
Logic Block Diagram
Media Access
Control Processor
Network
Processor
Application
Processor
2 KB RAM
2 KB EEPROM
10 KB ROM
Communication
Port
I/O Block
2 Timer/
Counters
Oscillator,
Clock, and
Control
LVD
Internal
Data Bus
(0:7)
Address Bus
(0:15)
Internal
CP4
CP0
IO10
IO0
CLK1
CLK2
/SERVICE
/RESET
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