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參數資料
| 型號： | CY5474FCT543T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit Latched Registered Transceiver |
| 中文描述： | 8位鎖存注冊收發器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 73K |
| 代理商： | CY5474FCT543T |
8-Bit Latched Registered Transceiver
CY54/74FCT543T
SCCS030 - May 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 5.3 ns max. (Com’l)
FCT-A speed at 6.5 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
ESD > 2000V
Sink current
64 mA (Com’l), 48 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
Separation controls for data flow in each direction
Back to back latches for storage
Extended commercial range of
40C to +85C
Functional Description
The FCT543T octal latched transceiver contains two sets of
eight D-type latches with separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) controls for each set to
permit independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B enable (CEAB) input must be LOW in order to enter
data from A or to take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal on the A-to-B latch
enable (LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their output no longer
change with the A inputs. With CEAB and OEAB both LOW,
the three-stage B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses CEAB, LEAB, and OEAB inputs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
LE
D Q
LE
D
Q
DetailA
DetailA x 7
A
0
A
2
A
1
A
3
A
4
A
5
A
6
A
7
B
0
B
2
B
1
B
3
B
4
B
6
B
5
B
7
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
Functional Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
LEBA
LEAB
CEBA
CEAB
OEBA
OEAB
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
CEBA
15
SOIC/QSOP
Top View
LEBA
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
OEBA
A
0
B
0
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