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| 型號： | CY54FCT245TSOIC |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit Transceiver |
| 中文描述： | 8位收發(fā)器 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 91K |
| 代理商： | CY54FCT245TSOIC |
8-Bit Transceiver
CY54/74FCT245T
SCCS018 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT, and
F logic
FCT-D speed at 3.8 ns max. (Com’l),
FCT-C speed at 4.1 ns max. (Com’l),
FCT-A speed at 4.6 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
ESD > 2000V
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Extended commercial range of
40C to +85C
Sink current
64 mA (Com’l), 48 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT245T contains eight non-inverting bidirectional buff-
ers with three-state outputs and is intended for bus oriented
applications. For the FCT245T, current sinking capability is 64
mA at the A and B ports.
The Transmit/Receiver (T/R) input determines the direction of
data flow through bidirectional transceiver. Transmit (Active
HIGH) enables data from A ports to B ports. The output enable
(OE), when HIGH, disables both the A and B ports by putting
them in a High Z condition.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Function Table
[1]
OE
L
L
H
T/R
L
H
X
Operation
B Data to Bus A
A Data to Bus B
High Z State
Note:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.
LogicBlockDiagram
Pin Configurations
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
OE
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
T/R
4
8
9
10
11
12
13
7
6 5
1516 17 18
3
2
1
20
19
14
A
A
A
B1
B4
B0
B
7
B
6
V
CC
OE
GND
B3
Top View
A
LCC
T/R
A
0
A
1
A
7
B
5
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
OE
15
Top View
B2
A
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
T/R
GND
DIP/SOIC/QSOP
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