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參數資料
| 型號： | CY54FCT273TQSOP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Bit Register |
| 中文描述： | 8位寄存器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 78K |
| 代理商： | CY54FCT273TQSOP |
8-Bit Register
CY54/74FCT273T
SCCS020 - March 1995 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 5.8 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
ESD > 2000V
Fully compatible with TTL input and output logic levels
Extended commercial range of
40C to +85C
Sink current
64 mA (Com’l), 32 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT273T consists of eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
flip-flops simultaneously. The FCT273T is an edge-triggered
register. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corre-
sponding flip-flop’s Q output. All outputs will be forced LOW by
a low voltage level on the MR input.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Note:
1.
H
h
L
l
X
= HIGH Voltage Level steady state
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
= LOW Voltage Level steady state
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
= Don’t Care
= LOW-to-HIGH clock transition
Logic Block Diagram
D
0
PinConfigurations
FCT273T–1
CP
D
Q
Q
0
R
D
CP
D
Q
D
1
Q
1
R
D
CP
D
Q
D
2
Q
2
R
D
CP
D
Q
D
3
Q
3
R
D
CP
D
Q
D
4
Q
4
R
D
CP
D
Q
D
5
Q
5
R
D
CP
D
Q
D
6
Q
6
R
D
CP
D
Q
D
7
Q
7
R
D
CP
MR
FCT273T–2
4
8
9
10
11
12
13
7 6 5
1516 1718
3
2
1
20
19
14
D
D
Q
D6
D5
D7
CP
Q
4
V
CC
Q
7
GND
Q5
Top View
D
LCC
MR
Q
0
D
0
Q
3
D
4
1
2
3
4
5
6
7
8
9
10
11
12
16
15
17
18
19
20
13
14
V
CC
Q
7
FCT273T–3
Top View
Q6
Q
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
CP
MR
GND
DIP/SOIC/QSOP
FCT273T–4
CP
MR
Q
0
D
0
D
1
Q
1
D
2
Q
2
D
3
Q
3
D
4
Q
4
D
5
Q
5
D
6
Q
6
D
7
Q
7
Logic Symbol
Function Table
[1]
Operating Mode
Reset (clear)
Load ‘1’
Load ‘0’
Inputs
CP
X
Output
Q
L
H
L
MR
L
H
H
D
X
h
l
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