
8-Bit Buffers/Line Drivers
CY54/74FCT540T
CY54/74FCT541T
SCCS029 - May 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 4.1 ns max. (Com’l)
FCT-A speed at 4.8 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
ESD > 2000V
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Sink current
64 mA (Com’l), 48 mA (Mil)
Source current
32 mA (Com’l), 12 mA (Mil)
Extended commercial range of
40C to +85C
Functional Description
The FCT540T inverting buffer/line driver and the FCT541T
non-inverting buffer/line driver are designedto be employed as
memory address drivers, clock drivers, and bus-oriented
transmitters/receivers. The devices provide speed and drive
capabilities
equivalent
to
counterparts while reducing power dissipation. The input and
output voltage levels allow direct interface with TTL, NMOS,
and CMOS devices without external components.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
their
fastest
bipolar
logic
Logic Block Diagram—FCT540T
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
OE
B
15
CERDIP/SOIC/QSOP
Top View
GND
O
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE
B
OE
A
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
OE
A
FCT540T
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
OE
B
15
CERDIP/DIP/SOIC/QSOP
Top View
GND
O
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE
B
OE
A
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
OE
A
Logic Block Diagram—FCT541T
FCT541T