
8-Bit Latches
CY54/74FCT373T
CY54/74FCT573T
SCCS021 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function and pinout compatible with FCT, and F logic
FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
ESD > 2000V
Matched rise and fall times
Extended commercial range of
40C to +85C
Fully compatible with TTL input and output logic levels
Sink current
64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organized applications. When latch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
15
17
18
19
20
13
14
V
CC
O
7
DIP/SOIC/QSOP
Top View
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
16
15
17
18
19
20
13
14
V
CC
O
0
DIP/SOIC/QSOP
Top View
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
OE
GND
LE
OE
O
0
D
0
D
1
O
1
D
2
O
2
D
3
O
3
D
4
O
4
D
5
O
5
D
6
O
6
D
7
O
7
CP
D
Q
O
0
D
0
LE
OE
CP
D
Q
O
1
D
1
CP
D
Q
O
2
D
2
CP
D
Q
O
3
D
3
CP
D
Q
O
4
D
4
CP
D
Q
O
5
D
5
CP
D
Q
O
6
D
6
CP
D
Q
O
7
D
7
FCT373T
FCT573T
Logic Symbol