
10-Bit Buffer
CY54/74FCT827T
SCCS034 - September 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function,pinout,anddrivecompatiblewithFCT,F,and
AM29827 logic
FCT-C speed at 4.4 ns max. (Com’l)
FCT-A speed at 5.0 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
ESD > 2000V
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Sink current
64 mA (Com’l),
32 mA (Mil)
32 mA (Com’l),
12 mA (Mil)
Source current
Functional Description
The FCT827T 10-bit bus driver provides high-performance
bus interface buffering for wide data/address paths or buses
carrying parity. The 10-bit buffers have NAND-ed output
enables for maximum control flexibility. The FCT827T is
designedforhigh-capacitanceloaddrivecapability,whileproviding
low-capacitancebusloadingatbothinputsandoutputs.Alloutputs
are
designed
for
low-capacitance
high-impedance state and are designed with a power-off disable
feature to allow for live insertion of boards.
bus
loading
in
the
Logic Block Diagram
Pin Configurations
Y
0
OE
1
Y
1
Y
2
Y
3
Y
4
Y
5
Y
8
Y
9
Y
6
Y
7
D
0
D
1
D
2
D
3
D
4
D
5
D
8
D
9
D
6
D
7
28
27
26
4
3
2
1
5
6
7
8
9
10
13
14
15
16
17
18
25
24
23
22
21
20
11
12
19
D4
D
D
Y
Y
N
N
Y
D
LCC/PLCC
Top View
NC
OE
2
GND
Y4
V
CC
Y
0
D
8
D
9
Y
8
Y
9
D
D
NC
OE
2
Y
Y
D
0
OE
1
D
1
Y
1
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
Y
0
15
SOIC/QSOP
Top View
OE
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
OE
2
GND
Function Table
[1]
Inputs
OE
2
L
L
X
H
Outputs
Y
L
H
Z
Z
Function
Transparent
OE
1
L
L
H
X
D
L
H
X
X
Three-State
Note:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care