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參數資料
| 型號： | CY62126DV30LL-45ZSXI |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT00; Number of Contacts:32; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:18-32 |
| 中文描述： | 1兆位（64K的× 16）靜態RAM |
| 文件頁數： | 1/11頁 |
| 文件大小： | 398K |
| 代理商： | CY62126DV30LL-45ZSXI |
1-Mbit (64K x 16) Static RAM
CY62126DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05230 Rev. *E
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 2, 2005
Features
Very high speed: 45 ns
Wide voltage range: 2.2V to 3.6V
Pin compatible with CY62126BV
Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Also available in Lead-free packages
Functional Description
[1]
The CY62126DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
2048 x 512
I/O
0
–I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
–I/O
15
CE
WE
BHE
A
0
A
9
A
10
相關PDF資料 |
PDF描述 |
|---|---|
| CY62126DV30LL-55ZSXI | 1-Mbit (64K x 16) Static RAM |
| CY62126DV30LL-55BVI | 1-Mbit (64K x 16) Static RAM |
| CY62126DV30L-70ZSI | 1-Mbit (64K x 16) Static RAM |
| CY62126DV30L-55ZSI | 1-Mbit (64K x 16) Static RAM |
| CY62126DV30L-70BVI | 1-Mbit (64K x 16) Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62126DV30LL-55BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 1M-Bit 64K x 16 55ns 48-Pin FBGA |
| CY62126DV30LL-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 1M-Bit 64K x 16 55ns 48-Pin FBGA T/R |
| CY62126DV30LL-55BVI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY62126DV30LL-55BVXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62126DV30LL-55ZI | 制造商:Cypress Semiconductor 功能描述: |
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