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參數(shù)資料
| 型號(hào)： | CY62127V-70ZC |
| 英文描述： | x16 SRAM |
| 中文描述： | x16的SRAM |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 153K |
| 代理商： | CY62127V-70ZC |
256K x 16 Static RAM
CY62147V18 MoBL2
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 6, 2000
Features
Low voltage range:
—CY62147V18: 1.75V–1.95V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62147V18 is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL) in por-
table applications such as cellular telephones. The devices
also have an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH) or when CE is LOW and both BLE and
BHE are HIGH. The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147V18 is available in 48-ball FBGA packaging.
MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Logic Block Diagram
256K x 16
RAM Array
2048 x 2048
I/O
0
– I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
– I/O
15
CE
WE
BHE
A
1
A
1
A
0
A
1
A
9
Power
-
Down
Circuit
BHE
BLE
CE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62127VL-55BAC | x16 SRAM |
| CY62127VL-55ZC | x16 SRAM |
| CY62128-70ZAC | x8 SRAM |
| CY62128-70ZAI | x8 SRAM |
| CY62128-70ZI | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127VL-55BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127VL-55ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127VL-70BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127VL-70ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62127VLL-55BAC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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