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參數(shù)資料
| 型號： | CY62128DV30L-55SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1 Mb (128K x 8) Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.450 INCH, SOIC-32 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 196K |
| 代理商： | CY62128DV30L-55SI |
1 Mb (128K x 8) Static RAM
CY62128DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05231 Rev. *C
Revised August 29, 2003
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Features
Very high speed: 55 and 70 ns
Wide voltage range: 2.2V to 3.6V
Pin compatible with CY62128V
Ultra-low active power
—Typical active current: 0.85 mA @ f = 1 MHz
—Typical active current: 5 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE
1
, CE
2
, and OE
features
Automatic power-down when deselected
Packages offered in a 32-lead SOIC, a 32-lead TSOP, a
32-lead Short TSOP, and a 32-lead Reverse TSOP
Functional Description
[1]
The CY62128DV30 is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life
(MoBL
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable 1
(CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW. The input/output
pins (I/O
0
through I/O
7
) are placed in a high-impedance state
when: deselected Chip Enable 1 (CE
1
) HIGH or Chip Enable
2 (CE
2
) LOW, outputs are disabled (OE HIGH), or during a
write operation (Chip Enable 1 (CE
1
) LOW and Chip Enable 2
(CE
2
) HIGH and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW with Chip Enable 2 (CE
2
) HIGH and Write En-
able(WE) LOW. Data on the eight I/O pins is then written into
the location specified on the Address pin (A
0
thro. A
16
).
Reading from the device is accomplished by taking Chip En-
able 1 (CE
1
) LOW with Chip Enable 2 (CE
2
) HIGH and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
o
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH) or
during a write operation (CE
1
LOW, CE
2
HIGH), and WE
LOW).
Note:
1.
For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
1
A
A1
A3
A4
A5
A6
A7
A8
A9
A10
A11
COLUMN
R
S
Data in Drivers
down
WE
OE
I/O0
I/O1
I/O2
I/O3
128K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
A
A
A
CE
1
CE
2
相關PDF資料 |
PDF描述 |
|---|---|
| CY62128DV30L-55ZAI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30L-55ZI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30L-55ZRI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30L-70SI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30L-70ZAI | 1 Mb (128K x 8) Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128DV30L-55SIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin SOIC T/R |
| CY62128DV30L-55ZAI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk |
| CY62128DV30L-55ZAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin STSOP-I T/R 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Tape and Reel |
| CY62128DV30L-55ZI | 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk |
| CY62128DV30L-55ZRI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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