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參數資料
| 型號： | CY62128EV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1 Mbit (128K x 8) Static RAM |
| 中文描述： | 1兆位（128K的× 8）靜態RAM |
| 文件頁數： | 1/11頁 |
| 文件大?。?/td> | 861K |
| 代理商： | CY62128EV30 |
1 Mbit (128K x 8) Static RAM
CY62128EV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05579 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 07, 2007
Features
Very high speed: 45 ns
Temperature ranges–
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
Wide voltage range: 2.20V – 3.60V
Pin compatible with CY62128DV30
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 4
μ
A
Ultra low active power
— Typical active current: 1.3 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin
STSOP packages
Functional Description
[1]
The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8 bits. This device
features advanced circuit design to provide ultra low active
current. This is ideal for providing More Battery Life (MoBL
)
in portable applications such as cellular telephones. The
device also has an automatic power down feature that signifi-
cantly reduces power consumption when addresses are not
toggling. Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW). The eight input and output pins (IO
0
through
IO
7
) are placed in a high impedance state when the device is
deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE
1
LOW and
CE
2
HIGH and WE LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins is then written into the location specified on the
Address pin (A
0
through A
16
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A
S
POWER
DOWN
WE
OE
A
A
A
A
R
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
CE1
CE2
Note
1. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
http://www.cypress.com.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62128EV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mbit (128K x 8) Static RAM |
| CY62128EV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128 K × 8) Static RAM Typical standby current: 1 μA |
| CY62128EV30_1106 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected |
| CY62128EV30LL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected |
| CY62128EV30LL-45AKJ | 制造商:Cypress Semiconductor 功能描述: |
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