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參數資料
| 型號： | CY62138CV30LL-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M (256K x 8) Static RAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 55 ns, PBGA36 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-36 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 234K |
| 代理商： | CY62138CV30LL-55BVI |
2M (256K x 8) Static RAM
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Cypress Semiconductor Corporation
Document #: 38-05200 Rev. *D
3901 North First Street
San Jose
CA 95134
Revised September 20, 2002
408-943-2600
Features
Very high speed: 55 ns and 70 ns
Voltage range:
—
CY62138CV25: 2.2V
–
2.7V
—
CY62138CV30: 2.7V
–
3.3V
—
CY62138CV33: 3.0V
–
3.6V
—
CY62138CV: 2.7V
–
3.6V
Pin-compatible with CY62138V
Ultra low active power
—
Typical active current: 1.5 mA @ f = 1 MHz
—
Typical active current: 5.5 mA @ f = f
max
(70-ns
speed)
Low standby power
Easy memory expansion with CE
1
, CE
2
, and OE
features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 36-ball FBGA
Functional Description
[1]
The CY62138CV25/30/33 and CY62138CV are high-perfor-
mance CMOS static RAMs organized as 256K words by eight
bits. This device features advanced circuit design to provide
ultra-low active current. This is ideal for providing More Battery
Life
(MoBL
) in portable applications. The device also has
an automatic power-down feature that significantly reduces
power consumption by 80% when addresses are not toggling.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected (CE
1
HIGH
or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
See the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
Note:
1.
For best practice recommendations, please refer to the Cypress application note
“
System Design Guidelines
”
on http://www.cypress.com.
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
1
CE
2
相關PDF資料 |
PDF描述 |
|---|---|
| CY62138CV30LL-70BAI | 2M (256K x 8) Static RAM |
| CY62138CV30LL-70BVI | 2M (256K x 8) Static RAM |
| CY62138CV33 | 2M (256K x 8) Static RAM |
| CY62138CV33LL-55BAI | 2M (256K x 8) Static RAM |
| CY62138CV33LL-55BVI | 2M (256K x 8) Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62138CV30LL-55BVIT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY62138CV30LL-55BVXI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 2MBIT 256KX8 55NS 36BGA - Bulk |
| CY62138CV30LL-55BVXIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 2MBIT 256KX8 55NS 36FBGA - Tape and Reel |
| CY62138CV30LL-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
| CY62138CV30LL-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2M (256K x 8) Static RAM |
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