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參數資料
| 型號： | CY62147CV18LL-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, FBGA-48 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 272K |
| 代理商： | CY62147CV18LL-55BVI |
256K x 16 Static RAM
CY62147CV18 MoBL2
Cypress Semiconductor Corporation
Document #: 38-05011 Rev. *B
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised October 31, 2001
Features
High Speed
—
55 ns and 70 ns availability
Low voltage range:
—
CY62147CV18: 1.65V
1.95V
Pin Compatible w/ CY62147V18/BV18
Ultra-low active power
—
Typical Active Current: 0.5 mA @ f = 1 MHz
—
Typical Active Current: 2 mA @ f = f
max
(70 ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62147CV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life
(MoBL
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can also be put into standby mode when deselect-
ed (CE HIGH or both BLE and BHE are HIGH). The input/out-
put pins (I/O
0
through I/O
15
) are placed in a high-impedance
state when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are dis-
abled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62147CV18 is available in a 48-ball FBGA package.
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Logic Block Diagram
256K x 16
RAM Array
2048 X 2048
I/O
0
–
I/O
7
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
8
–
I/O
15
OE
WE
A
1
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
8
Power
-
Down
Circuit
BHE
BLE
CE
A
9
A
10
A
1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62147CV18LL-70BAI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY62147CV18LL-70BAIT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Cypress Semiconductor 功能描述: |
| CY62147CV18LL-70BAXI | 制造商:Cypress Semiconductor 功能描述: |
| CY62147CV18LL-70BKI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62147CV18LL-70BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256K x 16 Static RAM |
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