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參數資料
| 型號： | CY62148DV30L-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mb (512K x 8) MoBL Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 55 ns, PBGA36 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-36 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 195K |
| 代理商： | CY62148DV30L-55BVI |
4-Mb (512K x 8) MoBL
Static RAM
CY62148DV30
Cypress Semiconductor Corporation
Document #: 38-05341 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 10, 2004
Features
Very high speed: 55 ns
—Wide voltage range: 2.20V – 3.60V
Pin-compatible with CY62148CV25, CY62148CV30 and
CY62148CV33
Ultra low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Typical active current: 8 mA @ f = f
max
(55-ns speed)
Ultra low standby power
Easy memory expansion with CE
,
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered: 36-ball BGA, 32-pin TSOPII and
32-pin SOIC
Functional Description
[1]
The CY62148DV30 is a high-performance CMOS static RAMs
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Note:
1.
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
CE
A
1
A
1
A
1
A
1
A
1
相關PDF資料 |
PDF描述 |
|---|---|
| CY62148DV30L-55BVXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55SXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55ZSXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-70BVI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-70BVXI | 4-Mb (512K x 8) MoBL Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY62148DV30L-55BVXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55SXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62148DV30L-55SXIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62148DV30L-55ZSXI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62148DV30L-70BVI | 制造商:Rochester Electronics LLC 功能描述:4MB (512KX8) SRAM SLOW 3.0V LOW POWER - Bulk |
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