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參數(shù)資料
| 型號： | CY62157CV30LL-70BAE |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 16 Static RAM |
| 中文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 328K |
| 代理商： | CY62157CV30LL-70BAE |
512K x 16 Static RAM
CY62157CV30/33
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 31, 2006
Features
Temperature Ranges
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
Voltage range:
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = f
max
Low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Available in Pb-free and non Pb-free 48-ball FBGA
package
Functional Description
[1]
The CY62157CV30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life
(MoBL) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standby mode reducing power consumption by more than 99%
when deselected (CE
1
HIGH or CE
2
LOW or both BLE and
BHE are HIGH). The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE
1
LOW and CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
18
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip
Enable 2 (CE
2
) HIGH while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
The CY62157CV30/33 are available in a 48-ball FBGA
package.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
512K × 16
RAM Array
I/O
0
–I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
I/O
8
–I/O
15
WE
BLE
BHE
A
1
A
0
A
1
A
9
A
1
A
10
Power-down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62157CV30LL-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 8M-Bit 512K x 16 70ns 48-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62157CV30LL-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 8M-Bit 512K x 16 70ns 48-Pin FBGA T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY62157CV33LL-55BAI | 制造商:Cypress Semiconductor 功能描述: |
| CY62157CV33LL-55BAIT | 制造商:Cypress Semiconductor 功能描述: |
| CY62157CV33LL-70BAI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:8MB (512KX16) SRAM SLOW 3.3V SUPER LOW POWER - Bulk |
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