
1024K x 8 MoBL Static RAM
CY62158CV25/30/33
MoBL
Cypress Semiconductor Corporation
Document #: 38-05019 Rev. *C
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised April 24, 2002
Features
High Speed
—
55 ns and 70 ns availability
Voltage range:
—
CY62158CV25: 2.2V
–
2.7V
—
CY62158CV30: 2.7V
–
3.3V
—
CY62158CV33: 3.0V
–
3.6V
Ultra low active power
—
Typical active current: 1.5 mA @ f = 1 MHz
—
Typical active current: 5.5 mA @ f = f
max
(70 ns speed)
Low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62158CV25/30/33 are high-performance CMOS static
RAMs organized as 1024K words by 8 bits. This device fea-
tures advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life
(MoBL
)
in portable applications such as cellular telephones. The de-
vice also has an automatic power-down feature that signifi-
cantly reduces power consumption by 80% when addresses
are not toggling. The device can be put into standby mode
reducing power consumption by more than 99% when dese-
lected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip En-
able 1 (CE
1
) and Output Enable (OE) LOW and Chip Enable
2 (CE
2
) HIGH while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
The CY62158CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
1024K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
CE
1
CE
2