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參數(shù)資料
| 型號(hào)： | CY62168DV30LL-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (2M x 8) MoBL㈢ Static RAM |
| 中文描述： | 2M X 8 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 8 X 9.50 MM, 1 MM PITCH, VFBGA-48 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 305K |
| 代理商： | CY62168DV30LL-55BVI |
16-Mbit (2M x 8) MoBL
Static RAM
CY62168DV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05329 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 27, 2006
Features
Very high speed
— 55 ns
Wide voltage range
— 2.2V – 3.6V
Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f
Max
(55 ns Speed)
Ultra-low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Available in Pb-free and non Pb-free 48-ball VFBGA
package
Functional Description
[1]
The CY62168DV30 is a high-performance CMOS static RAMs
organized as 2048Kbit words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 90% when
addresses are not toggling. The device can be put into standby
mode reducing power consumption by more than 99% when
deselected Chip Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
)
LOW. The input/output pins (I/O
0
through I/O
7
) are placed in
a high-impedance state when: deselected Chip Enable 1
(CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW, outputs are disabled
(OE HIGH), or during a write operation (Chip Enable 1 (CE
1
)
LOW and Chip Enable 2 (CE
2
) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address
pins(A
0
through A
20
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) and Output Enable (OE) LOW and Chip
Enable 2 (CE
2
) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
Logic Block Diagram
Note:
1. For best-practice recommendations, please refer to the Cypress application note entitled
System Design Guidelines
, available at http://www.cypress.com.
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
COLUMN
R
S
Data in Drivers
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
2048K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
CE
1
CE
2
A
2
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62168DV30LL-55BVIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 3.0V SUPER LO PWR 2MEGX8 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62168DV30LL-55BVXI | 功能描述:IC SRAM 16MBIT 55NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY62168DV30LL-55BVXIT | 功能描述:IC SRAM 16MBIT 55NS 48VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY62168DV30LL-70BVI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 16M-Bit 2M x 8 70ns 48-Pin VFBGA |
| CY62168DV30LL-70BVXI | 制造商:Cypress Semiconductor 功能描述: |
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