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參數資料
| 型號： | CY62177DV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (2M x 8) Static RAM |
| 中文描述： | 16兆位（2米× 8）靜態RAM |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 856K |
| 代理商： | CY62177DV30 |
Cypress Semiconductor Corporation
Document #: 001-07721 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 07, 2007
CY62168EV30 MoBL
16-Mbit (2M x 8) Static RAM
Features
Very high speed: 45 ns
Wide voltage range: 2.20V – 3.60V
Ultra low standby power
— Typical standby current: 1.5
μ
A
— Maximum standby current: 12
μ
A
Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power down when deselected
CMOS for optimum speed/power
Offered in Pb-free 48-ball FBGA package. For Pb-free
48-pin TSOP I package, refer to CY62167EV30 data sheet.
Functional Description
[1]
The CY62168EV30 is a high performance CMOS static RAM
organized as 2M words by 8 bits. This device features
advanced circuit design to provide an ultra low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. Placing the device into standby mode reduces power
consumption by more than 99% when deselected (Chip
Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW). The input
and output pins (IO
0
through IO
7
) are placed in a high
impedance state when: the device is deselected (Chip Enable
1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW), outputs are
disabled (OE HIGH), or a write operation is in progress (Chip
Enable 1 (CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and WE
LOW).
Write to the device by taking Chip Enable 1 (CE
1
) LOW and
Chip Enable 2 (CE
2
) HIGH and the Write Enable (WE) input
LOW. Data on the eight IO pins (IO
0
through IO
7
) is then
written into the location specified on the address pins (A
0
through A
20
).
Read from the device by taking Chip Enable 1 (CE
1
) and
Output Enable (OE) LOW and Chip Enable 2 (CE
2
) HIGH
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when the device is deselected (CE
1
LOW and CE
2
HIGH), the outputs are disabled (OE HIGH), or
a write operation is in progress (CE
1
LOW and CE
2
HIGH and
WE LOW). See the
“Truth Table” on page 8
for a complete
description of read and write modes.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
S
POWER
DOWN
WE
OE
A
A
A
A
R
COLUMN DECODER
2M x 8
ARRAY
DATA IN DRIVERS
A
CE1
CE2
A
A
A
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines
.
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相關代理商/技術參數 |
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